16b0d8f1e4
Disable the code that halts secondary processors in cpu_reboot(). Halting
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the secondary works, but not when called from here?! XXX!
1998-09-29 21:59:33 +00:00
ce57c93ef5
some temporary debugging printfs in the IPI code.
1998-09-29 19:40:33 +00:00
fb345194ad
document CLOCK_COMPAT_OSF1
1998-09-29 18:25:54 +00:00
70d1e71ea0
Allow to use the RTC chip in a way compatible to OSF/1: use an offset
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of 52 years between RTC and UNIX time.
This is controlled by "option CLOCK_COMPAT_OSF1".
1998-09-29 18:23:55 +00:00
88b626a585
make compile w/o MULTIPROCESSOR
1998-09-29 15:55:47 +00:00
55df520938
Can't use -traditional; __RENAME() breaks due to a limitation in the
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"traditional" C preprocessor.
1998-09-29 08:28:20 +00:00
5a5380b92b
This program is icky, and will die soon. So, don't put a whole lot of
...
effort into it, but make it build again by casting the second arg to signal().
1998-09-29 08:27:36 +00:00
005af97f9e
Use "print-objdir".
1998-09-29 08:16:11 +00:00
69d81d8df1
Prototype cpu_halt_secondary().
1998-09-29 07:07:36 +00:00
30e4de5632
In cpu_reboot(), halt the secondary CPUs.
1998-09-29 07:07:09 +00:00
1b8e855f2a
First try at a HALT interprocessor interrupt handler.
1998-09-29 07:06:02 +00:00
94b97dce9b
CPUF_HATCHED is dead, replaced by cpus_running bitmask.
1998-09-29 07:05:30 +00:00
99698d1a1a
- Use a bitmask for "running CPUs", rather than a flag in the softc.
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- Add a function to halt a secondary CPU.
- Enable interrupts on secondary CPUs once they've hatched.
1998-09-29 07:04:58 +00:00
469f020ae3
Don't process CLOCK or DEVICE interrupts if we're not the primary CPU.
1998-09-29 07:02:04 +00:00
30ec5015b1
In exception_return(), if MULTIPROCESSOR, skip software interrupts, ASTs,
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and floating point handling if we're not the primary CPU.
1998-09-29 07:01:16 +00:00
392a96cc91
Define the offset of hwrpb->rpb_primary_cpu_id.
1998-09-29 06:22:09 +00:00
ce9e4beacf
Simplify the asm constraints in mrg_aline_super(), in order to
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less thoroughly confuse the compiler when used without -O. Fixes
PR 5496.
1998-09-29 05:24:08 +00:00
183f609c83
- Do not set TLCPUMASK on non-I/O nodes. That register exists only on
...
I/O nodes. Previous code erroneously set it on CPU nodes only.
- In both the single- and multi-processor case, route all interrupts from
I/O nodes to the primary CPU, for now.
1998-09-29 04:22:36 +00:00
3c2e2c8622
This should need opt_execfmt.h.
1998-09-28 23:42:48 +00:00
4c2e179b93
PROM doens't need to be mapped to start up the secondaries, so remove some
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dead code.
1998-09-28 22:21:13 +00:00
9bd45385a9
Turn off some debugging printfs, and kludge around a boot block bug until
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I can install fixed boot blocks on my MP test systems.
1998-09-28 21:50:32 +00:00
705cac105e
Invalidate the TB and I-stream upon entry, and fix a typo in the wrkgp call.
1998-09-28 21:48:50 +00:00
34a8ac8484
Set the primary CPU's PAL revision to the OSF/1 PAL revision after switching
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to it, per the Green Book (pointed out by Chris Demetriou).
1998-09-28 21:21:55 +00:00
5caecb6ae0
Fix for some EGCS warnings.
1998-09-28 21:18:55 +00:00
fd24065cb5
pcvt is no longer used with bebox.
1998-09-28 09:49:49 +00:00
4a04e5038e
pcvt is no longer used with bebox.
1998-09-28 09:33:12 +00:00
e30046b37d
This was a copy of an very old editing error in the amiga pmap.c....
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(Ignatios Souvatzis)
1998-09-28 07:51:23 +00:00
980b2b416f
fix PMAP_ACTIVATE_ASN_SANITY() arguments
1998-09-27 17:23:25 +00:00
8c29324cc7
Kernel configuration with multi-processor support.
1998-09-27 15:10:25 +00:00
a965fe73b1
Add support for the TFL LAN Inc. E410/E420 PDS cards. Based on code
...
from Ken Nakata in PR 6199, which was in turn derived from code from
Haru Maruyama <h-maru @ da2.so-net.ne.jp>.
1998-09-27 14:39:11 +00:00
0a090af2c7
Add `ldstub()'.
1998-09-27 14:32:14 +00:00
e6ce8bcfc7
sparc spin lock functions.
1998-09-27 14:31:18 +00:00
b7f86e40fa
The smallest positive normalized number in extended precision is 2^-16383.
...
Underflow handling is different from i387.
1998-09-27 04:54:49 +00:00
463301afbf
Use common date conversion functions - not runtime efficient, but
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brain-efficient...
1998-09-26 21:02:56 +00:00
1826b0bca2
Use the RTC chip as time-of-year clock, as the PROM console and Ultrix do.
1998-09-26 20:59:42 +00:00
0a1a6fb7e0
This file is no longer used
1998-09-26 20:51:45 +00:00
166c2a5fa5
fix typo
1998-09-26 20:15:59 +00:00
9f352b7e15
Stop all other CPUs upon entering a debugger.
1998-09-26 20:14:48 +00:00
01e64c640c
Implement mp_pause_cpus() and mp_resume_cpus(): pause and resume all
...
CPUs except the one running this code.
1998-09-26 20:13:56 +00:00
6ad3a051e8
mp_{pause,resume,halt}_cpu() prototypes.
1998-09-26 20:12:06 +00:00
6eb98a7967
4/NPTEPG is 0. This is a very old editing error.
1998-09-26 19:26:58 +00:00
029ab07a4d
delint
1998-09-26 19:21:19 +00:00
8ddcd514a6
Use CPU start function in obp.c
1998-09-26 19:09:56 +00:00
fe1cf94b9f
Add wrappers for PROM's CPU start/stop functions.
1998-09-26 19:08:09 +00:00
a89a10c394
Add file obp.c
1998-09-26 19:06:47 +00:00
43c1cb852c
Move PROM interface prototypes into openprom.h
...
Use the `openprom_addr' structure for passing around physical addresses.
1998-09-26 18:20:19 +00:00
09a4cf6caa
Move PROM interface routines into their own file.
1998-09-26 18:15:34 +00:00
d208510692
Add support for AdvanSys Ultra Wide boards
1998-09-26 16:38:43 +00:00
87fab23d68
make it compile with DEBUG
1998-09-26 10:07:36 +00:00
b356238b16
Add one more new MIPS processor PRid 0x30 for IDT RC64474/64475. These
...
are successors of RC4640/RC4650, but fully brewed MIPS, then capable of
running NetBSD/mips.
1998-09-26 08:16:38 +00:00
7af1966350
Regenerate from podules.
1998-09-26 03:30:50 +00:00
3da75bb55d
Update the list of MIPS processor revision ID. PRids of Toshiba TX3900
...
and QED R4650 comflict each other.
1998-09-26 03:29:37 +00:00
a96d8e733a
Add EESOX manufacturer ID and SCSI2 podule ID.
1998-09-26 03:29:36 +00:00
2c50ec242f
Add basic interprocessor interrupt sending and receiving code. Current
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IPI functions: HALT, IMB, TBIA, TBIAP.
XXX HALT is not yet implemented, it's just a stub.
1998-09-26 00:03:51 +00:00
78d445810b
Add an interprocessor interrupt bitmask to the cpu_softc, and publicize
...
the cpus[] array.
1998-09-26 00:01:17 +00:00
1f4921edce
- Oops, forgot to initalize the cpu_softc simplelock.
...
- Add yet another debugging printf.
1998-09-26 00:00:33 +00:00
e2aa38459c
Implement atomic quadword load-and-latch.
1998-09-25 23:59:42 +00:00
01c75223d7
Minor style tweaks.
1998-09-25 22:06:33 +00:00
eb8de83739
`eccmemctl' inadvertently got into the `mandatory' list.
1998-09-25 11:40:16 +00:00
d3ce2be01c
Don't bother printing the message from the secondary console. All it is
...
is basically the acknowledgement of the START command. Print the idle
USPACE address for now. Use the alias "apcb_backup_ksp" when setting the
backup kernel stack pointer in the secondary's boot HWPCB.
1998-09-25 03:23:50 +00:00
57e656b2ec
The processor unique value in the PCB is used as a backup kernel stack
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pointer when booting secondary CPUs. Add an alias for it.
1998-09-25 03:21:31 +00:00
3ea9247ac8
GENERIC config file + MULTIPROCESSOR + some debugging stuff.
1998-09-25 00:46:09 +00:00
fcb0203141
First-cut at code to spin up secondary processors on a multiprocessor
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Alpha system, conditional on MULTIPROCESSOR.
NOTE: This does not yet work completely. The secondary CPU begins the
boot process, but never makes it into the cpu spinup trampoline. This
is merely a snapshot of a work-in-progress.
1998-09-24 23:28:17 +00:00
feb1d22dcc
NCPU > 1 -> MULTIPROCESSOR
1998-09-24 23:00:43 +00:00
3cde5f5817
Machine-dependent spin lock operations for Alpha, included if MULTIPROCESSOR
...
is specified.
1998-09-24 22:32:35 +00:00
91a031471d
Implement atomic test-and-set for longwords (32-bit).
1998-09-24 22:22:07 +00:00
1b04ff4897
Make prom_enter() and prom_leave() public.
1998-09-24 21:18:13 +00:00
ba6d13d876
Use the primary CPU ID on console_restart(), not hard-coded 0.
1998-09-24 21:12:43 +00:00
27569e4050
Initialize pointer to the boot CPU's interrupt register.
1998-09-24 20:38:43 +00:00
831354d6de
Add `intreg' cpuinfo offset.
1998-09-24 20:37:17 +00:00
e43333b7e7
Move if_ade* from alpha/pci/ to alpha/a12/
1998-09-24 05:36:05 +00:00
09c3723e08
Put back ahc and bha scsi HBA driver configs.
1998-09-24 05:33:41 +00:00
81ea242049
Fix include path, these days a12 header files are in alpha/a12.
1998-09-24 05:32:52 +00:00
ec4de2679b
Track tfs -> ustarfs change.
1998-09-24 05:23:58 +00:00
c69dbb3c28
Actually, yes we do know what the rpb_restart entry point is used for,
...
so delete some #if 0'd code.
1998-09-24 03:39:24 +00:00
7521c309df
When setting up the hwrpb for restarts, use the primary CPU ID from the
...
hwrpb.
1998-09-24 00:30:19 +00:00
7df5ebc392
"Gee, there was already a function to do that."
1998-09-23 22:02:21 +00:00
53d42701b5
Implement a function to recompute the HWRPB checksum.
1998-09-23 21:51:04 +00:00
86f044d10e
Track changes elsewhere in the PCI interface.
1998-09-23 21:20:55 +00:00
55714d5b34
Update for vm_offset_t, vaddr_t sweep.
1998-09-23 21:17:17 +00:00
ddde99135e
A12 crossbar switch driver.
1998-09-23 21:14:58 +00:00
73fdd29a64
A12 detached console tty driver and NetBSD console interface.
1998-09-23 21:14:02 +00:00
58ab38cb69
Use per-CPU interrupt status register.
1998-09-23 11:07:28 +00:00
9eca565a37
Make cgsix_sbus & cgsix_obio dependent on their respective attribute.s
1998-09-23 08:49:46 +00:00
d6746389a4
The nmi_* routines are sun4m-only.
1998-09-23 08:44:51 +00:00
d720002637
Fix a typo in RCS keyword.
1998-09-22 16:23:20 +00:00
7c4c19c768
First pass KNF. This probably needs more work.
1998-09-22 16:01:51 +00:00
aa1cf01930
Express per-processor interrupt registers in a C structure as well.
1998-09-22 13:42:26 +00:00
bd37118769
Dup header.
1998-09-22 13:41:03 +00:00
eca50c1c33
Flush cache after diddling with trap vectors.
1998-09-22 13:40:08 +00:00
1186ba5102
Introduce a `flush entire cache' method.
1998-09-22 13:39:19 +00:00
5afb0e8bcb
Keep the per-processor interrupt status in the cpuinfo structure.
...
For now, map them to the fixed virtual addresses set up early in autoconf.c
1998-09-22 13:08:44 +00:00
5fa16c668b
Define the inter-console communication buffer portion of the per-cpu
...
info structure.
1998-09-22 08:16:51 +00:00
ec49dd71dd
Change 41 separate printf()'s into a table and 2 printf()'s.
1998-09-22 06:24:26 +00:00
6871d2529f
Add missing mb ops.
1998-09-22 06:10:53 +00:00
402a9210a2
Implement quadword atomic test-and-set.
1998-09-22 05:56:52 +00:00
c945760779
sign-extend some operand types which need it.
1998-09-22 05:40:14 +00:00
5b01d45ac4
Add a `-b #' option and logic for locating the secondary boot image via
...
an absolute block address. It's cheating, as the motivation is support for
the libsa ustar tfs `filesystem' and the solution symmetrical to ufs and
cd9660 would have been to teach installboot about tfs. However, it still
would have been different as you can't mount a tfs with the kernel, and
this option gets possibly useful support for any contiguous format, even
completely raw boot images.
1998-09-22 05:03:36 +00:00
e10cc7910d
Add some support for multiple processors to the pmap module. Still left
...
to do: TLB shootdown code, but that will be much easier to write once
the code to spin up the additional CPUs is working.
1998-09-22 03:58:10 +00:00
bc3dce964b
Declare the coda character device functions here.
1998-09-22 03:42:10 +00:00
thorpej