- hpc1_hdd_{ctl,bufptr} and hpc3_hdd_{ctl,bufptr} are
established in hpcreg.h. All references to these fields
are updated with the exception of if_sq: (haltwo,
hpcdma). This makes reading the code and spotting bugs
easier.
- hpcdma.c was applying EOCHAIN to the wrong descriptor
word for the hpc1 case.
- I added scsi_max_xfer to the abstraction layer, and it
allows some crusty #defines in wdsc.c to be removed.
hpc1 now doesn't waste descriptors as it once did.
- hpcreg.h was updated to reflect the lack of XMITDONE
bit in hpc1. HPC1_REV15 added for a test in hpc.c
- hpc.c now verifies HPC1 revisions (1.0 vs 1.5) and
prints the output a little prettier ;)
- power interrupts shouldn't establish on non-IP22
platforms.
divergence between HPC revision 1.5 and revision 3.
The wdsc driver has been updated to reflect this layer (and may now work on
IP20). The sq driver needs a bit more work before it can be committed.
DMA register offsets, as well as IRQ, to children. Use direct
config. Use machine type/subtype to determine which devices are
present.
* Add support for the second SCSI controller on the Indigo2.
the controller/SCSI bus.
* Implement controller/SCSI bus reset on SGI HPC3 SCSI using the
"channel reset" bit in the SCSI DMA channel control register.
Based on mvme68k and Atari drivers for the same chipset with the
addition of bus_space support. Attempts have been made to seperate out the
machine dependent dma components and more work is required in this area.
Tested on SGI R4K Indy, but has little testing on other platforms.
