Commit Graph

62724 Commits

Author SHA1 Message Date
maxv
3b60a5c86e Define tablesize. Useful when debugging. 2016-05-29 09:16:11 +00:00
maxv
17a417d61a Revert rev1.94. It apparently raises a page fault from SMEP. I need to
investigate the whole kernel mappings anyway, so I'll recommit this
patch later.
2016-05-29 09:04:19 +00:00
sevan
32e3745627 As instructed by Martin@, disable DKWEDGE_METHOD_APPLE for now as it causes a
fresh install in a dual boot scenario to fail. This is because fstab will be
referencing wd(4) and the kernel expecting dk(4).

Closes PR port-macppc/51160
2016-05-28 22:24:51 +00:00
maxv
fd2c2b78c0 Define fillkpt_blank, which creates blank entries in a page table. Use
it to map the first MB. No functional change.
2016-05-28 09:03:16 +00:00
maxv
79fe8af4b4 Move proc0's stack out of the BOOTSTRAP TABLES, and map it independently
with RW permissions. Reduces the impact of a stack overflow.
2016-05-28 08:43:16 +00:00
bouyer
bdf10c852a The UART in the allwiner SoCs is not full-compatible with the 16550, and
it's not a 16750 either. Like the 16750 it has the IIR_BUSY interrupt,
which is triggered when writing to LCR while the chip
can't accept it. But unlike the 16750, it has a specific register,
HALT, to allow writing to the LCR and divisor registers, and then
commit the changes.
Tested on an A20 SoC, changing the baud rate while keeping the
tty device open and incoming data.
2016-05-27 20:01:49 +00:00
macallan
f9df4180d4 treat IPIs like regular interrupts at IPL_HIGH
should fix port-powerpc/44387
tested by chuq
2016-05-26 17:38:05 +00:00
nakayama
4645840d5b Add more CardBus devices. 2016-05-26 10:38:07 +00:00
bouyer
727b83213d Remove a KASSERT() which is A20-specific, as well as the local variable
used here.
Fix "error: unused variable 'grp'" for non-DIAGNOSTIC kernels,
reported by Rin Okuyama.
2016-05-26 07:45:51 +00:00
maxv
a56d0ceb2a There is an issue in the way the fillkpt macro sets up pages on both
amd64 and i386.

The fillkpt loop is equivalent to the following:

	do {
		/* fill in the slot */
		/* increment %ebx to the next slot */
		/* increment %eax to the next pa */
	} while (%ecx > 0)

The issue here is that if %ecx = 0 (i.e., the chunk we are trying to
map is zero-sized), there is still one entry created in the page table.
The kernel expects the va<->pa translation to be linear in low memory.
If there is a zero-sized chunk, the dead entry creates a +4096 offset in
the virtual space, with two consecutive entries that point to the same
physical address. In other words, the mappings are not linear anymore,
which causes the kernel to die.

Before my recent changes, there were only two big chunks that were
mapped, and neither of these could be zero-sized. Now, with multiple,
fine-grained chunks, it is possible that the [SYMS]+[PRELOADED_MODULES]
chunk could be zero-sized.

[PRELOADED_MODULES] is almost never here, and [SYMS] is always here on
default kernels. Except for floppies, where the bootloader does not load
[SYMS].

Should fix PR 51148.
2016-05-26 07:24:55 +00:00
nakayama
cb7479712f sort 2016-05-26 04:26:05 +00:00
nakayama
f1700a0c7a tabify, fix indent and remove trailing whitespace. 2016-05-25 20:00:50 +00:00
martin
87669b78b9 Update comment explaining why PAX_MPROTECT is disabled here 2016-05-24 13:57:26 +00:00
martin
ffb79a8f7b New Rawrite32 release 2016-05-23 18:36:05 +00:00
jmcneill
84e0ecfe04 IST_MPSAFE is not a valid flag for fdtbus_intr_establish; use
FDT_INTR_MPSAFE instead.
2016-05-23 18:21:14 +00:00
chs
72af35a796 remove unused variables. 2016-05-23 01:45:41 +00:00
maxv
7123eade7b Save L4's physical address earlier. Also, PDE_SIZE has nothing to do
here, we are just zeroing out the upper 32bits of the 64bit pointer.
2016-05-22 10:11:55 +00:00
christos
2b0df44082 Account for the VA hole differently (simpler) 2016-05-22 01:09:09 +00:00
christos
bfab48c6b3 Add various security options; enables PaX ASLR/MPROTECT 2016-05-21 18:31:13 +00:00
maxv
c4cd7f0720 There is an issue in the way the direct map is set up on amd64.
When allocating memory, the kernel allocates physical pages and virtual
addresses for these pages. In order to optimize allocations smaller
than PAGE_SIZE, uvm_km_kmem_alloc can allocate a single physical page
and take its virtual address in the direct map in high virtual memory.
This direct map is set up at boot time, its PTEs do not change, and
therefore they don't need to be kentered. These high virtual PTEs being
constant, the permissions of the areas they point to are fixed at boot
time and cannot change.

The problem is that at boot time, they are created with RWX permissions.
Therefore, allocations smaller than PAGE_SIZE in the kernel heap are all
executable: mbufs, pnbufs, small kmem allocations, etc.

Fix this by setting the NOX bit in the direct map pages at boot time. We
also set the NOX bit in the temporary tmpva, since it does not need to
be executable either.

This also makes the U-area non executable on amd64.
2016-05-21 07:15:56 +00:00
maxv
d1afa69a65 Explain where this value comes from. 2016-05-21 07:00:18 +00:00
christos
9930e8e348 gcc can't compute the large initializer in rpi_release_mem,
so disable stack protector.
2016-05-20 16:40:40 +00:00
jnemeth
605ea3fe8e make CPU microcode loading dependent on both DOM0OPS AND CPU_UCODE 2016-05-20 03:41:20 +00:00
christos
5fbd96fa60 Turn on PaX ASLR/MPROTECT 2016-05-20 01:37:47 +00:00
christos
7b6e3dab7a We don't want PIE! 2016-05-19 15:41:18 +00:00
christos
48f9de0fc1 Turn on ASLR for sparc64 2016-05-19 15:37:06 +00:00
christos
9b7590baea lose one more bit of ALSR to account for rounding in the VA hole. 2016-05-19 15:36:35 +00:00
ryo
5ca0adf8c7 delete unused variables 2016-05-19 05:15:51 +00:00
nakayama
10bacc40a1 Decrement %tl in trap handler not to make it zero unconditionally
for the nested trap, and remove useless mov.
2016-05-18 15:14:08 +00:00
nakayama
da6c94469a Fix (unused) pstate mask bits in tstate and comment. 2016-05-18 07:59:30 +00:00
palle
2f23095fbd sun4v: Implement missng MMU protection trap handling - mostly from OpenBSD 2016-05-17 19:43:28 +00:00
palle
61ea5f5e14 Update TODO: sun4v_datatrap handling for trap level 0 is working 2016-05-17 19:39:44 +00:00
msaitoh
7ca43d6799 Fix CORTEXA9Rx definitions. 2016-05-17 08:27:24 +00:00
ryo
ec48232126 Add initial support for Freescale i.MX7 SoC and
Atmark Techno Armadillo-IoT G3 boards.

Contributed by Internet Initiative Japan Inc.
2016-05-17 06:44:45 +00:00
christos
10c1bb4dec Clamt the PAX_ASLR random value to the max bits we have for VA. 2016-05-17 00:39:43 +00:00
palle
ef44ed55df Avoid assembler-specific defines by using the export keyword in genassym.cf instead 2016-05-16 20:03:07 +00:00
maxv
9c4befc9b2 Update kern.ldscript.4MB. It is the same as kern.ldscript, but with a large
page alignment before rodata.
2016-05-16 07:52:31 +00:00
nakayama
49bc961c13 %g1 is not preserved across function call, so load it before
return_from_trap.
2016-05-15 23:54:58 +00:00
chs
6ee802c24a define ALTENTRY(), needed by dtrace. 2016-05-15 15:26:04 +00:00
maxv
9aca421dba Explicitly mention MP_TRAMPOLINE in these comments, so that NXR links them. 2016-05-15 10:35:54 +00:00
maxv
4c1aaf9dc6 Split the PRELOADED_MODULES+BOOTSTRAP_TABLES chunk into two separate
chunks mapped independently with RWX and RW, on both amd64 and i386.

This way the BOOTSTRAP TABLES are non-executable.
2016-05-15 07:17:53 +00:00
maxv
0d0621d260 Reduce the diff between amd64 and i386. We invert two instructions on
amd64, but it makes no difference since PDE_SIZE = 8.
2016-05-15 07:01:36 +00:00
christos
931302e025 Turn on MPROTECT on GENERIC and both MPROTECT and ASLR on XEN* 2016-05-14 17:11:30 +00:00
maxv
b561cb98a5 KNF so it appears aligned on NXR, and fix a comment. 2016-05-14 12:48:31 +00:00
maxv
8f728b8ede Actually, put the NOX identification above. Old CPUs do not support the
cpuid instruction.
2016-05-14 09:51:56 +00:00
maxv
15756d7e09 The NOX bit on large pages does not need to be amd64-specific anymore.
The i386 secondary CPUs can now properly handle it.
2016-05-14 09:37:21 +00:00
maxv
f63de3d1a3 Map rodata and data+bss independently, and give them R and RW with
fillkpt_nox. The code is exactly the same as amd64's.
2016-05-14 08:49:16 +00:00
maxv
e39b2c82ed Define fillkpt_nox on i386, same as amd64.
But there is a difference in the way it is done here. If PAE is not enabled,
PDE_SIZE = 4, so there is no NOX bit set. If PAE is enabled, PDE_SIZE = 8,
so the NOX bit is set.

This works exactly as intended, since NOX does not exist in the non-PAE
case.
2016-05-14 08:39:41 +00:00
maxv
9d6cfafacd Fix the secondary CPUs bug in i386. Same as amd64. 2016-05-14 08:34:00 +00:00
maxv
3b5965adb8 Align the segments on i386. We're going to map them independently. 2016-05-14 08:19:42 +00:00