Page mod/ref status is stored in the pv header, and needs to be copied to
the following entry when removing the head entry, otherwise the status
will be lost (oops!).
Move the common MIPS3 cache flush into pmap_remove_pv() and eliminate the
unnecessary testing of the return value when only compiled for MIPS1.
If the pv entry had the cache inhibited, and we remove the last cache index
alias conflict, restore caching on the mappings for that entry.
Eliminate possible extra cache flushing inherited from the pica pmap: it
was doing the flush when the head entry was being removed - not just the last
entry. Now the flush is done only when the last mapping has been removed.
Also make sure the secondary cache gets flushed [MIPS3 cache flushing needs
to be re-thought/re-done someday].
Update comment for pmap_remove_pv() to reflect these changes.
original debug output was printing the argument to pmap_create(), but
pmap_create() no longer has an argument. The incorrect change now prints
an un-initialized pointer. Change to just print out the function name.
to allow this exception so that accurate tuning of delay() can be
done (i.e. avoiding VIA-related wait states and cache effects as
much as possible).
XXX During this narrow window, it is still conceivable that we could
get interrupts from devices other than the VIA timer. Normally this
shouldn't be a problem because interrupt handlers should generally
not be registered until we get to autoconfig. It is, however, a
potential pitfall to be aware of.
any longer, we can finally avoid enabling interrupts until the
end of cpu_configure(). This resolves a long-standing issue that
has caused us trouble several times in the past.
don't panic if maxlen == 0, just return ENAMETOLONG.
treat maxlen as unsigned like the manpage indicates.
avoid crashing if the userspace address is >= KERNBASE.
make sure *done is 0 when no bytes are copied.
cache. With secondary cache, the CPU will detect cache coherency errors
and the Virtual Coherency Exception handler will flush the appropriate
cache lines to maintain cache coherency. This allows much better
performance than inhibiting the cache for the entire page. This is
very noticable when shared library mappings occur with incompatible
mappings, since there's a very likely chance the mappings will remain
for long periods of time. Systems without secondary cache will still
have the cache inhibited, so there will still be performance issues if
shared libraries don't get mmaped() on correct memory alignments.
This fixes the current problems on DECstations using the R4x00 getting
coredumped programs.
