Commit Graph

34355 Commits

Author SHA1 Message Date
pk
4d7731a177 cpu_switch:
* return `switched to same process' only if that process was actually
  already on a run queue when we entered.
* skip the switch to the idle stack if we can switch immediately
* .. and because of this, don't release the scheduler lock until after
  we've fully switched to the new process's stack.
2003-01-17 14:49:45 +00:00
pk
d352e8ce9c pmap_deactivate(): only update the pmap's cpuset if need to. 2003-01-17 14:15:17 +00:00
nonaka
f843b3302c Fix compile failure. 2003-01-17 13:27:56 +00:00
nonaka
0a4b06a4b4 Fix bus_space_mmap() bug.
> Module Name:    src
> Committed By:   augustss
> Date:           Sun Jan 12 23:46:12 UTC 2003
>
> Modified Files:
> 	src/sys/arch/pmppc/pmppc: bus_space.c
>
>Log Message:
>The bus_space_mmap() returns a physaddr, not a page, on the PPC.
>(This is broken in some (all?) of the PPC ports, it seems.)
2003-01-17 13:19:25 +00:00
simonb
b2e8253950 Zero out the TX buffer when padding packet to ETHER_MIN_LEN-ETHER_CRC_LEN. 2003-01-17 12:40:20 +00:00
pk
1d67b9c75a Don't grab the kernel lock for system timer interrupts; this mostly prevents
stalls in system time processing.

XXX - deal with non-atomic global time variables updates later.
2003-01-17 10:36:19 +00:00
lonewolf
628ec7a152 Compiles and works (tested on my A1200) again
XXX scsipi mid layer spews out a few "generic HBA error"s during device probe (no slave device on bus), I don't know how to fix this
XXX This whole thing should die now that we have wdc_amiga
2003-01-17 04:20:38 +00:00
petrov
6383ae6ccb Don't do anything if there are no streaming buffer cache. 2003-01-16 21:55:52 +00:00
pk
2252ed574d mp_{pause,resume,halt}_cpus(): check for cpus==NULL. 2003-01-16 17:21:43 +00:00
pk
c454f450b1 Define a MP version of callrom(). 2003-01-16 16:58:52 +00:00
pk
7d4c3f7430 Remove some accidental garbage. 2003-01-16 16:58:23 +00:00
pk
72c28f7bb7 Rename the current mp_{pause,resume}_cpus() => mp_{pause,resume}_cpus_ddb().
Implement mp_pause_cpus/mp_resume_cpus on top of the PROM services.
2003-01-16 16:57:43 +00:00
pk
58b50d0643 Read the CPU mailbox in the level 15 soft interrupt handler and respond
to idle and stop requests.
2003-01-16 16:27:48 +00:00
pk
b418a6a59d Some PROMs get really uneasy if the prom_reboot() function is called
after the other CPUs have already return into the PROM through prom_cpustop().
So don't do it; try to halt the other CPUs only when an actual `halt'
is requested.

My guess in this case is that the PROM does not expect its original boot
CPU to call prom_cpustop(0), or possibly treats it as the equivalent of
a prom_halt() which is then called again by some other CPU. In any case,
the result is garbage.
2003-01-16 16:20:20 +00:00
pk
f312ee5f9a What do you know.. the prom_cpu{stop,idle,resume} function appear to be
returning a success/fail flag. For now, use it to be informative.
2003-01-16 16:10:44 +00:00
scw
b8b3ddc479 Add a "kernel_text" label.
Pointed out by Andrew Brown.
2003-01-16 15:52:53 +00:00
pk
5e231ddd1c * Implement mp_halt_cpus()
* xcall: use printf_nolog()
2003-01-16 14:49:08 +00:00
pk
72286d4202 Definitions of some OBP generated CPU mailbox messages. 2003-01-16 14:43:07 +00:00
pk
26fa27a910 Fix reboot options handling; now one-letter kernel names can also be booted. 2003-01-16 11:33:21 +00:00
matt
0ccdd339c8 A small LP64 fix. 2003-01-16 09:17:01 +00:00
matt
76fda2e342 Add ISA Floppy (to be consistent with INSTALL). 2003-01-16 07:23:06 +00:00
matt
81d3f59353 Add PLATFORM_IBM_6040 2003-01-16 06:59:19 +00:00
petrov
b5be66abcd Move dump_dtlb back under DDB. 2003-01-16 03:01:23 +00:00
matt
72020abb85 Add platform support for the IBM PPS Model 6040 (E) (aka ThinkPad 820). 2003-01-16 02:18:20 +00:00
simonb
c018fbe68d Tidy up event counter increments a little. 2003-01-16 01:14:17 +00:00
simonb
c69f520bc8 Removed unused register map; this info is now passed in with the attach
args.
2003-01-16 01:05:39 +00:00
pk
a5cea9e740 On Hypersparc MP machines, we need to flush the TLB after a page cache flush.
While the pmap functions take care of properly ordering cache and TLB flushes,
not all TLB flush requests are sent to all CPUs (due to per CPU pmap tracking)
while cache flushes are always broadcast.

XXX: need to investigate pmap tracking for cache flush operation as well.
2003-01-15 22:56:32 +00:00
bouyer
bcae687139 Zero out the NIC memory when padding packet to ETHER_MIN_LEN-ETHER_CRC_LEN
sc->write_mbuf now return len of buffer, including padding.
Tested with a PCI ne2000.
2003-01-15 22:20:03 +00:00
pk
5bb3d93538 srmmu_cache_flush: switch MMU contexts in all places where it matters.
(incidentally, this also makes Hypersparc MP machines mostly go).
2003-01-15 16:42:27 +00:00
reinoud
e2dacd3f22 Small typo and add initialisation for the `bank' counter 2003-01-15 16:29:27 +00:00
mhitch
7295f9f909 Switch to MI installboot. 2003-01-15 07:25:51 +00:00
pk
a458d9f040 Fix compiler warning induced by last change. 2003-01-15 06:57:12 +00:00
chs
0d8f526f58 fix two bugs in my last pmap rework:
- in tlb_flush_all(), don't skip TLB entries with the high bit on,
   I was confused about which MMU register it was using.  it's also fine
   to use the last hardware context.
 - in pmap_create(), don't allocate a hardware context for the new pmap.
   it's unnecessary, and when this would cause us to recycle all the contexts,
   it would result in the current process's context being set to 0
   (ie. the kernel's context).  the current process could then return to
   userspace without going through the context-switch code (and thus without
   having a hardware context reallocated).  this would lead to user mappings
   being entered in the kernel's context later, causing all sorts of trouble.
   add some assertions to catch this kind of thing.
2003-01-15 06:15:05 +00:00
thorpej
c8763685b7 Allow the serial console boot blocks to be built with a specific
console speed, and build some of the more common ones.
2003-01-14 23:53:30 +00:00
thorpej
f6f0dbd011 Stub out LIBCRT0, LIBCRTBEGIN, LIBCRTEND, and LIBC. 2003-01-14 23:51:34 +00:00
pk
9eb63b3b94 statintr: if interrupting code running below IPL_SCHED, call schedintr()
directly, saving the overhead of an extra soft interrupt.
2003-01-14 23:00:59 +00:00
pk
c8226e1ce0 Define spllowerschedclock().
To be used in the same spirit as spllowersoftclock().
2003-01-14 22:58:00 +00:00
pk
d45f77c6c8 Add CLKF_LOPRI() macro that allows a (timer) interrupt handler to determine
whether it is interrupting code running at a given IPL level.
2003-01-14 22:54:53 +00:00
pk
ee7e8274a6 xcall: raise IPL to splsched() to prevent interrupts that take schedlock.
Otherwise we have a locking order problem with schedlock and xmsglock.
2003-01-14 17:30:55 +00:00
pk
18cd92ffe3 (Re)initialise the pmap structure fields that are not preserved on the
pmap pool cache all in one place.
2003-01-14 13:56:07 +00:00
fvdl
5692526bb6 Remove duplicate assignment. 2003-01-14 11:13:25 +00:00
fvdl
d928619394 Add a couple more ServerWorks host bridges that explicitly need IO space
enabled.
2003-01-14 10:56:53 +00:00
fair
7b889057b4 Add bktr*, udsbr* and radio* at each;
allocate a major number for radio*
2003-01-14 08:40:53 +00:00
fvdl
28c12bee16 Actually return the number of found PCI interrupt routes in mpacpi_pcircount
(doh). From Wolfgang Solfrank.
2003-01-13 21:14:39 +00:00
bouyer
3075f204fd As pceb pulls in sio.c and sio_pci.c, is also needs the alpha_shared_intr
attribute.
2003-01-13 20:55:14 +00:00
augustss
12a30d35ea Add KGDB (commented out). 2003-01-13 20:48:16 +00:00
augustss
cb7fde57d3 Make it compile on MPC6xx. I'm not sure about MPC40x. 2003-01-13 20:29:34 +00:00
augustss
5e9e39026f Add KGDB hooks. 2003-01-13 20:26:44 +00:00
augustss
fdac9a76f1 Enable nested interrupts. 2003-01-13 20:26:22 +00:00
pk
b50058b483 Broadcast I-cache flush in the `Unimplemented Flush' trap handler. 2003-01-13 20:00:34 +00:00