8d9571d120
remove cpu_hatched, cpu_hatch_sc and cpu_hatchstack. the first can use
...
the cpi->flags, the second is unused and the third is also cpi-idle_u.
2003-01-13 15:50:50 +00:00
5642428f4e
Use print_nolog() from xcall(), to avoid confounding things even further
...
by re-entering the scheduling code to wakeup syslog waiters.
2003-01-13 15:01:16 +00:00
4641d55697
Halt any other CPUs in cpu_reboot().
2003-01-13 01:35:45 +00:00
2684c88122
fpulock: encapsulate required IPL raise in the FPU LOCK/UNLOCK macros.
2003-01-12 16:29:00 +00:00
24780840a1
Account softintr_common as uvmexp.softs, not uvmexp.intrs.
2003-01-12 06:11:01 +00:00
55a3bd0a85
schedcpu() has been fixed; now we can notify another CPU about a pending
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reschedule request.
2003-01-12 01:50:51 +00:00
c41718e9ec
Remove needless indirection from the curproc() macro.
2003-01-12 01:19:00 +00:00
ae33d2b4e5
Use per-CPU virtual addresses for pmap_copy_page() & pmap_zero_page().
2003-01-12 01:16:06 +00:00
dab556c2b1
pmap_deactivate(): arguments for sp_tlb_flush() were reversed.
2003-01-12 00:34:52 +00:00
90d9434890
keep track of which cpu's have run a pmap and only broadcast tlb flushes to
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cpu's who have done so. implement pmap_deactivate() for MULTIPROCESSOR and
call it from cpu_switch() when we are about to switch proces and when we
enter idle().
with this change, i see significantly reduced tlb IPI traffic and fork/exec
bound processes -- such as "configure" -- run significantly faster, upto
15%. i also obvserved a small (0-2%) benefit to CPU bound tasks as well.
2003-01-11 03:40:31 +00:00
e756303d08
expand db_proc_cmd() a little more.
2003-01-10 19:25:12 +00:00
30cc38bdb5
Replace `want_resched' and `want_ast' globals by per-CPU variables.
2003-01-10 16:34:14 +00:00
b346ea724a
Merge sparc and sparc64 <machine/signal.h>.
2003-01-09 23:25:24 +00:00
70628f1993
clean up db_proc_cmd() output slightly.
2003-01-09 18:00:51 +00:00
18c8de0d93
It's now required to turn off traps in the srmmu cache flush ops in
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non-MULTIPROCESSOR kernels too.
2003-01-09 12:29:52 +00:00
cbc8b8122d
Check for existing soft interrupts too before trying to install a fast
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interrupt handler.
2003-01-09 10:27:24 +00:00
ec9ebd1af6
- s/xpmsg11/xpmsg15/
...
- clean up
- no need to reset the msg.tag
2003-01-09 05:55:30 +00:00
7386726570
remove a line accidentally commited in previous.
2003-01-09 05:27:09 +00:00
9b0c7030f5
call splclock() around the FPU_LOCK().
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XXX: pk suggests we can make the this a sleeping lock.
2003-01-09 04:58:58 +00:00
f234ea91a2
Remove write_user_windows() from a number of `4m' functions, since we don't
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switch contexts with traps enabled anymore.
2003-01-08 18:46:28 +00:00
f63279a9b6
Add CPUINFO_WANT_RESCHED and CPUINFO_WANT_AST
2003-01-08 17:49:39 +00:00
87e0907cbb
Avoid external declaration for the dummy `ross_pend' variable.
2003-01-08 17:22:09 +00:00
127392a5b7
Prepare for per-CPU reschedule and AST requests.
2003-01-08 17:19:53 +00:00
d3db019efd
Make pv_uncache() and pv_cacheflush() static functions.
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Split pv_cacheflush() in sun4/sun4c and sun4m/sun4d versions.
2003-01-08 16:16:46 +00:00
f4018cde22
Initialise the secondary CPUs' `spc_runtime'.
2003-01-08 01:20:56 +00:00
88f08d9ac1
- add a new message tag for level15 software NMI, and switch ddb to use this
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rather than the level13 software intr xpmsg area. now DDB IPI's don't lock
the xpmsg_lock and we avoid recursion and more.
- don't actually use cpuinfo.msg.lock yet, xpmsg_lock suffices.
- reread the pending register on mbus hypersparc cpus to avoid bugs in the
h/w that cause IPI's to be missed.
2003-01-07 16:20:13 +00:00
02d686d112
Simplify ddb register storage setup: remove MULTIPROCESSOR special cases
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and keep the ddb register copies on the current stack always.
2003-01-07 16:03:03 +00:00
469014c2cd
* Maintain a pointer to the cpu_info structure of the CPU being examined.
...
* Force cpu_Debugger() to have a stack frame, so tracing can at least
start off matching arguments and function calls correctly.
2003-01-07 15:15:06 +00:00
004dd5ecba
#include <sys/kernel.h> for `cold'.
2003-01-07 13:12:59 +00:00
63b5299d1e
Let all CPUs play..
2003-01-07 12:09:00 +00:00
e1dfbff267
xcall: use splclock() to prevent interrupts that want the kernel lock.
2003-01-07 10:57:18 +00:00
141297688f
revert (most of) previous
2003-01-07 10:31:56 +00:00
c0338e49bf
don't do the xcall() dance on sun4d for the cache flushing, but do make
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sure we're only doing one flush at a time...
2003-01-07 05:57:37 +00:00
1035faff1d
writable, not writeable.
2003-01-06 20:30:28 +00:00
0a66c7efe5
Protect FPU context switching with its own lock.
2003-01-06 18:32:31 +00:00
4bb41ae2f2
Rework how KERNOBJDIR functions; now it's always determined with
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cd ${KERNSRCDIR}/${KERNARCHDIR}/compile && ${PRINTOBJDIR}
This is far simpler than the previous system, and more robust with
objdirs built via BSDOBJDIR.
The previous method of finding KERNOBJDIR when using BSDOBJDIR by
referencing _SRC_TOP_OBJ_ from another directory was extremely
fragile due to the depth first tree walk by <bsd.subdir.mk>, and
the caching of _SRC_TOP_OBJ_ (with MAKEOVERRIDES) which would be
empty on the *first* pass to create fresh objdirs.
This change requires adding sys/arch/*/compile/Makefile to create
the objdir in that directory, and descending into arch/*/compile
from arch/*/Makefile. Remove the now-unnecessary .keep_me files
whilst here.
Per lengthy discussion with Andrew Brown.
2003-01-06 17:40:18 +00:00
675149a358
- md_fpumid = -1 => md_fpu = NULL, in some #ifdef FPU_DEBUG code
...
- only call KERNEL_PROC_UNLOCK() if we called KERNEL_PROC_LOCK() originally.
2003-01-06 14:16:10 +00:00
67998a8646
Move schedintr() to clock.c and initialise schedhz in initclocks(), so
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these are available to all timer implementations.
2003-01-06 12:50:43 +00:00
9a9c991837
Fix SP tlb_flush_{ctx,all} macros.
2003-01-06 12:10:46 +00:00
9df7616ed3
Combine the various sun4m/sun4d TLB flush routines into a hand-coded
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assembler version.
2003-01-05 19:38:42 +00:00
c0142e4ded
Print the cpu number in many pmapdebug-controlled debug traces.
2003-01-05 19:31:12 +00:00
113229a2cb
trap(T_FPE): reset the `p_md.md_fpu' when preempting the FPU.
2003-01-05 19:26:17 +00:00
3e2e9af6c9
Grab the kernel lock on interrupts at level IPL_CLOCK and lower.
2003-01-04 19:25:36 +00:00
5e73320f0f
Re-arrange the fields in struct cpu_info such that the most heavily used ones
...
are together, to reduce cache stomping.
2003-01-04 18:54:45 +00:00
f6fc3bd5fc
new cpu_switch: SMP: even if we pick up the same process after idling, we
...
must reset its context as the process might have run on another cpu in
between and had its context changed, e.g. by exec(2).
2003-01-04 11:09:18 +00:00
277fb5e18a
remove a now bogus comment from xcall()
2003-01-03 16:27:23 +00:00
68da24bd3d
- remove some dead debug code
...
- don't cross call the smp_tlb_flush*() routines on SUN4D, just ensure
that there is only one concurrent flush happening.
2003-01-03 16:24:50 +00:00
fb1500c7e1
remove dead extern fpproc/foundfpu declarations.
2003-01-03 16:21:05 +00:00
5b23b7800a
FPU save is handled in xcall() now.
2003-01-03 16:20:21 +00:00
444faacaac
xcall(): consult the `cpuset' argument for posting the cross calls.
2003-01-03 15:49:11 +00:00
0a78c9e13a
Define a few XCALL? shorthand macros to avoid clutter.
2003-01-03 15:44:55 +00:00
ff451161e2
Finish FPU context switching on SMP systems.
2003-01-03 15:12:02 +00:00
87a073002c
Make the *_stream_* methods always use the *_real accessors.
...
Define __BUS_SPACE_HAS_STREAM_METHODS.
2003-01-03 13:23:39 +00:00
7bd617d237
part one of bus_space(9) fixes to enable bus spaces to override the
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bus_space_{read,write}_[1248]() functions, which will allow 16-bit
PCMCIA support to work without additional hacks in MI drivers.
this option is not enabled yet.
2003-01-03 11:57:45 +00:00
947028ed94
reverse mailbox physical address check: now warn if it's not I/O space.
2003-01-03 09:22:11 +00:00
3f5be1863e
srmmu cache flush: use to the CPU context parameter; this is now required.
2003-01-03 09:19:03 +00:00
c79ff46cb6
don't try to setup MXCC registers on non-primary CPU's on systems without
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SMP support.
2003-01-02 09:42:09 +00:00
9dd42c6155
SMP: lock kernel for soft interrupts < IPL_SCHED as well.
2003-01-01 16:17:10 +00:00
3607bd7dca
pmap_alloc_cpu: use flags from boot cpu for now, as the passed cpu_info
...
structure has not been fully setup yet.
2003-01-01 15:56:11 +00:00
16305a65cb
prom mailbox map: look for the property `mailbox-virtual' first.
2003-01-01 15:51:00 +00:00
2fff4ee989
fix a comment.
2003-01-01 08:24:48 +00:00
d06249b555
KNF.
2003-01-01 06:33:29 +00:00
9c1214153c
Use aprint_normal() for cfprint routines.
2003-01-01 02:20:47 +00:00
2aac3c7c89
Slight optimisation in proc_trampoline().
2002-12-31 17:07:36 +00:00
1df04e663f
Make the schedintr() code common for all timers.
2002-12-31 16:45:52 +00:00
7b7269ba42
New version of cpu_switch/switchexit, mostly to simplify SMP support. It's
...
currently conditional on ALT_SWITCH_CODE (defaults to `on' if MULTIPROCESSOR
is defined) until more testing rounds are completed.
2002-12-31 16:17:12 +00:00
3d8def4865
Use a soft interrupt scheme to schedule schedclock(), so we can make
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splsched() less than splhigh().
2002-12-31 15:57:26 +00:00
67e16e38a4
Define IPL_SCHED at level 11 and make splsched() use it.
2002-12-31 15:51:18 +00:00
d358537b64
Pass the CPU context to all TLB flush routines. Because of this (and the
...
fact that cache flushes are also passed the context number), most
"long-term" context switches can be eliminated from the SRMMU versions
of the pmap functions.
2002-12-31 15:23:29 +00:00
83dae8a821
* map the PROM CPU mailbox if available.
...
* map MXCC error/status registers if available.
* add MXCC-specific module error interrupt handler.
* use high priority interrupt level in mp_pause_cpus()
2002-12-31 15:10:28 +00:00
2b59d26892
Add offset for `cpuinfo.ci_tt'.
2002-12-31 15:05:48 +00:00
c3bb05ff5b
* Add level argument to raise_ipi()
...
* Add diagnostic field members to cpu_info.
2002-12-31 15:04:49 +00:00
5c671fd10d
nmi_sun4m: run handler at splhigh()
2002-12-31 14:34:54 +00:00
43b86d0b59
rwindow debug code: display the current cpu number.
2002-12-31 13:17:23 +00:00
a1e9e5cae8
Add some more definitions: SRMMU and MXCC reset register.
2002-12-31 12:01:27 +00:00
122353da40
rename CPU_READY() to CPU_NOTREADY() seeing that's what it checks.
2002-12-28 02:35:56 +00:00
7d51aacb32
update the vme bus_space_tag_t to reality.
2002-12-28 01:33:00 +00:00
ffbcb6d927
Conditionalize T_DBPAUSE trap handling on #ifdef MULTIPROCESSOR to make
...
single CPU kernels compile again.
2002-12-26 12:14:31 +00:00
f8055a350c
* Use correct PC value for displaying the called function.
...
* Merge code to display non-kernel frames.
2002-12-23 13:21:10 +00:00
f953a01835
xcallintr() receive a `clockframe *' argument, not a `trapframe *'.
...
Setup a DDB context for paused CPUs by defining a soft trap (T_DBPAUSE)
which uses the generic trap handler code to get the trapframe constructed
and then calls on a debugger-defined `suspend' routine.
2002-12-23 00:55:16 +00:00
5c62f82bdf
Upon trap exit, update the trapframe with data for the running CPU rather
...
than the one which was the last target of the `machine cpu' command.
2002-12-23 00:42:37 +00:00
6ee482ef5b
change what 'hw.model' reports to be more inline with other netbsd ports, as
...
well as reporting the actual machine model & cpu, rather than first configured
CPU. changes for two machines are:
old:
hw.model = TMS390Z50 v0 or TMS390Z55 @ 75 MHz, on-chip FPU
hw.model = SUNW,UltraSPARC @ 143.002 MHz, version 0 FPU
new:
hw.model = SUNW,SPARCstation-20 (TMS390Z50 v0 or TMS390Z55 @ 75 MHz, on-chip FPU)
hw.model = SUNW,Ultra-1 (SUNW,UltraSPARC @ 143.002 MHz, version 0 FPU)
as per discussion on port-sparc & port-sparc64.
2002-12-22 02:17:24 +00:00
4a06119a9d
Pass the system call table to trace_enter() and ktrsys() so that it is
...
possible to use alternate system call tables. This is usefull for
displaying correctly the arguments in Mach binaries traces.
If NULL is given, then the regular systam call table for the process is used.
2002-12-21 16:23:56 +00:00
4e0634669b
* xcallintr(): use cpuinfo directly again.
...
* nmi_soft(): remove most of the obsoleted requests.
2002-12-21 12:55:54 +00:00
0408b1cbc8
tlb_flush_segment() and tlb_flush_region() now take a virtual address
...
argument instead of segment and region numbers.
2002-12-21 12:52:55 +00:00
82815de0ad
Use xcall() to broadcast MMU TLB flushes.
2002-12-21 12:13:38 +00:00
8dcde9f5b1
* cpu_hatch(): enable interrupts upon return from cpu_setup().
...
* interrupt trap: acquire the kernel lock only for interrupt levels <= PIL_SCHED
2002-12-21 11:57:41 +00:00
1d8dc4daf2
* getcacheinfo_obp(): also initialise the cacheinfo i/d associativity fields
...
in the case of a unified cache.
* xcall(): slightly optimise the `wait for other CPUs' loop.
2002-12-21 11:48:55 +00:00
f0a20f1305
* mark selected fields of `struct xpmsg' as volatile, instead of the whole
...
structure.
* change volatile => __volatile
2002-12-19 16:31:38 +00:00
2fba4e01ff
Mark CPUs that did not spin up properly and don't enable them later on.
2002-12-19 11:20:30 +00:00
75c5f270d2
Brush-up the generic cross-call routine and use it to implement the SMP
...
cache flush ops.
Also a standard soft interrupt handler for standard cross-call notification
reserving the NMI level 15 softint for urgent cross calls.
2002-12-19 10:38:28 +00:00
eaf530d598
Sprinkle volatiles to avoid register allocation, esp. in cross-call
...
synchronisation functions used in SMP kernels.
2002-12-19 10:30:39 +00:00
ec2b1c3c64
smp_cache_flush() also takes a context parameter.
2002-12-19 10:27:19 +00:00
2076dbdb04
Install the sparc V8 multiply/divide routines after we've collected some
...
basic information on the CPUs.
2002-12-18 11:56:43 +00:00
1a854929dd
we use nmi_hard and nmi_soft on SUN4D as well
2002-12-18 06:20:36 +00:00
a26cbfba69
Deal with an `unimplemented flush' trap from kernel mode.
2002-12-17 10:04:19 +00:00
c2ddc52f2d
The cache flush routines now take a CPU context parameter. This is going
...
to be necessary in SMP kernels.
2002-12-16 16:59:09 +00:00
b036b089a7
Multiple inclusion protection.
2002-12-16 16:24:40 +00:00
0a3a2262cb
Increment version number for match function and Cycle 5 IP changes.
2002-12-16 13:02:58 +00:00
079b83cafa
Extend the matching routine to take a function pointer, so that additional
...
(arbitrary) matching can be done.
Add match function and patch for Cycle 5 IP (Sparc 5 clone).
Reviewed by Uwe.
2002-12-16 13:01:01 +00:00
mrg