early in boot and broken early in boot by requiring a partly static
structure with another structure that must be present by the time
any uses are performed. theoretically platform code could allocate
a chunk while seting up memory and assign it here, giving a dynamic
sizing for the entry list, but the reality is that all users have
a statically allocated entry list as well.
the existing KERNHIST_LINK_STATIC() is used in conjunction with
KERNHIST_INITIALIZER() instead.
this stops a NULL pointer deref when the _LOG() macro is called
before the storage is linked in, which happens with GCC 10 on OCTEON
with UVMHIST enabled, crashing in very early kernel init.
The panic occures in bus_space_barrier() in rk3399_pcie.c:rkpcie_conf_read().
We expected bus_space_peek_4() to trap and recover in the path
trap_el1h_sync() -> data_abort_handler(), but In fact, the read is delayed
until bus_space_barrier(), and we get an SError interrupt (trap_el1h_error)
instead of a Synchronous Exception (trap_el1h_sync).
To catch this correctly, An implicit barrier in bus_space_peek have been added,
and trap the SError interrupt to recover from.
Also, change load/store('l','s') to 'r','w' like the other arch.
>db{0}> machine watch/1 hostname
>Bad modifier
>db{0}> machine watch/s1 hostname
>add watchpoint 0 as ffffc00001087848
Limited support for hardware watchpoint has been available for some time, but it
has not been working properly. In addition, it stopped working at the time of
the PTRACE support commit on 2018-12-13. This has been fixed to work correctly,
and also fixed to be practical by sharing hardware watchpoints and breakpoints
between CPUs on MULTIPROCESSOR.
Also fixed a bug that causes a malfunction when switching CPUs with
"machine cpu N" when entering ddb mode from other than cpu_Debugger().
I have confirmed that the CPU can be switched by "machine cpu N" and return from
ddb properly in each case where ddb is called triggered by ddb break/watchpoint,
hardware break/watchpoint, and cpu_Debugger().
the previous state.
Use DISABLE_INTERRUPT_SAVE()/ENABLE_INTERRUPT() in pic_splfuncs instead
of cpsid()/cpsie(). The difference here is the caller no longer specifies
which bits to disable and enable; on arm32 we continue to use I32_bit and
on aarch64 we now consistently toggle both IRQ and FIQ state.
- in cpu_idle(), ci_intr_depth is always 0, so there is no need to fetch for increment or conditional branch.
- curcpu() is immutable in idle lwp, there is no need to consider KPREEMPT. Therefore, get curcpu() first and keep using it.
- add more comment.
the loop in pmap_page_remove() always removes the first pv,
and since the list is managed by _pmap_remove_pv(), pp->pp_pv.pv_next always points to the first.
gcc calls it as "_mconut", llvm calls as "__mcount".
Change the main name of mcount to "mcount()", and created "_mcount" and "__mcount" entries
to work regardless of which compiler the object was created with.
- add MCOUNT_ENTER, MCOUNT_EXIT macro
- __mcount() function should be aligned
- add "-fno-optimize-sibling-calls" option when PROF. for accurate profiling, it is better to suppress the tail call.
