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365 Commits

Author SHA1 Message Date
thorpej
fe8841f18a Some platforms, like the Sable, hook EISA and ISA interrupts 
up Very Differently.  Handle this.
 2000-06-13 16:40:37 +00:00
thorpej
75975dd6c5 G/c some unneeded prototypes (functions don't exist). 2000-06-11 22:47:00 +00:00
thorpej
f3d9d1ac8a Use the common 82c693 access functions to read/write the ELCR. 2000-06-06 03:10:13 +00:00
thorpej
f65502fc36 Report which compatibility IRQ the PCI IDE gets. 2000-06-06 00:50:15 +00:00
thorpej
b0ce38fd8a Switch to the new `evcnt' mechanism for counting interrupts. Maintain 
a per-CPU interrupt counter for clock, device, and interprocessor
interrupts.
 2000-06-05 21:47:26 +00:00
thorpej
2668e3b213 Switch to the new `evcnt' mechanism for counting interrupts. Maintain 
a per-CPU interrupt counter for clock, device, and interprocessor
interrupts.
 2000-06-05 21:47:10 +00:00
cgd
cffb580806 Implement the more flexiable `evcnt' interface as discussed (briefly) on 
tech-kern and now documented in evcnt(9).
 2000-06-04 19:14:14 +00:00
thorpej
9851571246 Add support for the Alpha Processor, Inc. UP1000 EV6 system. 2000-06-01 20:30:28 +00:00
drochner
13c9f8d398 implement bus_space_vaddr() 2000-04-17 17:24:48 +00:00
thorpej
156114a02f Use the new cpu_amask variable rather than calling alpha_implver() and 
alpha_amask() ourselves.
 2000-04-03 01:48:07 +00:00
thorpej
f785596e75 Add support for mapping the OHCI USB controller interrupt (which is wired toan ISA IRQ because it's in the same package as the PCI-ISA bridge). 2000-03-19 02:25:29 +00:00
thorpej
c10a9d31ea Put the code that enables/disables Pyxis interrupt lines in 
cia_pyxis_intr_enable().
 2000-03-19 01:43:25 +00:00
mycroft
cf3085176e Nuke all the code associated with the INITIALLY_LEVEL_TRIGGERED() lossage, and 
instead register a shutdownhook to restore the PIC state.
 2000-02-27 02:50:31 +00:00
thorpej
df88882d80 - Add a bus space method for getting the translation for a window. 
- Add sysarch methods for "get bus window count", "get bus window",
  and "pci conf read/write".

These are a hack, but they're what's necessary in order to make
XFree86 work in its current state.
 2000-02-26 18:53:10 +00:00
thorpej
de974ff82d Add an internal bus space method alpha_bus_space_translate(), which 
provides a method to translate an address on an I/O bus into a sysBus
address, along with acccess method information.
 2000-02-25 00:45:04 +00:00
mjacob
9621e6be50 Reset maxstray count if we get a good interrupt for a level. 2000-02-10 07:45:43 +00:00
mjacob
4821b5ae2f Guard against trying to disable an interrupt where we'd dereference a 
bad pointer.
 2000-02-10 04:31:36 +00:00
thorpej
f9e531f1e4 Don't force BWX on Pyxis by default; it's just not reliable enough. 2000-02-09 01:39:20 +00:00
thorpej
17c346b9e1 Changed cacheable -> prefetchable. [sync w/ swiz] 2000-02-06 04:07:18 +00:00
elric
28bdaf37d9 Changed cacheable -> prefetchable. 2000-02-06 03:52:27 +00:00
thorpej
97eba73a40 If we have a Pyxis with the DMA page crossing bug, don't allow coalescing 
of adjacent DMA segments.

XXX This is still not perfect... but making it perfect will probably
require additions to the bus_dma interface and the ISA autoconfiguration
interface.
 2000-02-06 01:26:50 +00:00
thorpej
0cf304bb45 Always use BWX for bus access on Pyxis chips. 2000-02-01 19:29:28 +00:00
thorpej
35f3518a91 Fix a fatal typo in a Pyxis SGMAP TLB bug workaround. Noticed by 
Jeff Roberson <nomad@nop.aliensystems.com>.
 2000-01-25 03:32:36 +00:00
thorpej
a5b316c4d5 Key off NSIO and NPCEB for (E)ISA interrupt support. 
XXX Can probably nuke the SIO test; don't all of the Noritake-class systems
XXX have EISA?
 1999-12-15 22:31:04 +00:00
thorpej
4f580f447c Key off NSIO and NPCEB for (E)ISA interrupt support. 
XXX Can probably nuke the SIO test; don't all of the Mikasa-class systems
XXX have EISA?
 1999-12-15 22:30:40 +00:00
thorpej
58a51e3b72 Key off NSIO and NPCEB for (E)ISA interrupt support. 
XXX Can probably nuke the SIO test; don't all of the ALCOR-class systems
XXX have EISA?
 1999-12-15 22:28:15 +00:00
thorpej
c557690acc Key off NSIO and NPCEB for (E)ISA interrupt support. 
XXX Can probably nuke the SIO test; don't all of the Rawhide-class systems
XXX have EISA?
 1999-12-15 22:25:21 +00:00
thorpej
3ffe65b597 Use alpha_shared_intr_{get,set}_private(). 1999-12-15 22:21:45 +00:00
thorpej
deed2b3b4b Fix a botch in stray interrupt reporting; report the kn300 IRQ, not the 
interrupt enable bit on the MCPCIA the interrupt is mapped to.
 1999-12-15 20:10:04 +00:00
thorpej
781149bb12 Handle the case where PCI dense memory and PCI sparse memory don't 
overlap; don't require allocation from the dense extent if the PCI
memory address isn't mapped into dense space.

Also, make sure to return an error if a liner mapping is requested
and dense space is not available (not just not requested).
 1999-12-08 01:48:39 +00:00
thorpej
9beb275ae8 Oops, committed the wrong version of this file previously. 1999-12-08 00:35:43 +00:00
thorpej
ac20942bc5 Some systems don't have dense space; don't require it. 1999-12-07 07:04:39 +00:00
thorpej
51f4c69ad4 Clarify what appear to the untrained eye to be two magic constants (the 
address shift and access size shift), and allow them to be overridden
by chip-specific code, if necessary.
 1999-12-07 05:44:57 +00:00
mjacob
d5e85e61cf Fixes PR#8836. Some changes made by somebody else were a tad incomplete so 
configuring w/o SIO broke compilation. I forget why, but there was at one
point (and may still be) a dependency between SIO and EISA. This change
just makes things compile sensibly again. It may make no sense to build
a kernel w/o sio in this case. I can't test this conveniently because I
haven't got a 4100 with a video card in it at the moment.
 1999-12-04 20:29:02 +00:00
thorpej
90bc415584 Pull in the BWX inlines. We expect the arch to be set appropriately for 
the assembler before these files are pulled in by the chip-sepecific files.
 1999-12-02 19:44:49 +00:00
thorpej
4e08cc6996 CIA core logic with BWX enabled appears on EV6. We require at least 
EV56 for the assembler to emit BWX opcodes, so set the arch to "ev6".
 1999-12-02 19:43:58 +00:00
thorpej
dc362cf369 CIA core logic with BWX enabled appears on both EV56 and PCA56. We 
require at least EV56 for the assembler to emit BWX opcodes, so set
the arch to "ev56".
 1999-12-02 19:43:25 +00:00
mjacob
ce28c5e558 Make sure a MCPCIA exists before trying to initialize it. Also make 
sure a MCPCIA softc exists before trying to do post-config cleanup
on it.
 1999-11-16 18:33:11 +00:00
lukem
0888d71168 recognise the ACER labs M1543 PCI-ISA Bridge in siomatch(). the DS10 now boots! 
thanks to thorpej/ross/mrg for helping me out on this.
 1999-11-12 22:07:28 +00:00
thorpej
06a4c7fe53 Allow rd/line, rd/mult, and wr/inval. 1999-11-04 19:15:22 +00:00
thorpej
a3759d67fe Don't do rd/line, rd/mult, or wr/inval on the buggy Miata 1's. 1999-11-04 19:11:51 +00:00
thorpej
1825cdf45b Tell the PCI layer that Memory Read Line, Memory Read Multiple, and 
Memory Write and Invalidate are okay PCI commands to use.
 1999-11-04 01:02:38 +00:00
ross
02140cb46f Fix the 16-bytes-of-death bug by generating specific-EOI cycles during 
sio_intr_setup().
 1999-07-30 20:33:43 +00:00
ross
ced3118f58 * sprintf -> snprintf 
* add a few alpha_mb() ops as called for by folklore and rumour
 1999-06-29 17:10:57 +00:00
ross
7a27e79bff Support for EV6 Tsunami core logic and system type 6600. 
This covers most or all of the presently-available 21264 systems.
 1999-06-29 06:46:46 +00:00
thorpej
3b29e1e158 Clean up the Rawhide interrupt code some more: 
- Actually display the kn300 irq, not the MCPCIA irq, in the interrupt
  string.  Also, don't bother displaying device/pin on strays, since
  it doesn't play will with shared interrupts that would happen due to
  a PCI-PCI bridge.
- Shave a few more cycles out of the interrupt dispatch routine.
 1999-04-16 21:29:47 +00:00
thorpej
d38cab08e5 Add SGMAP stuff for Window 2, and rename Window 0's SGMAP stuff to indicate 
its use.
 1999-04-16 02:18:07 +00:00
thorpej
1ddebc8444 Fix a silly bug present since rev 1.1; the direct-mapped window is 
supposed to be Window 1, but a cut'n'paste error made it stomp over
Window 0, thus breaking ISA DMA.  Fix this.  (Confirmed to work with
floppy driver.)

While I'm here, do something I've been meaning to do for a while: change
Window 1 from a 1G at 2G to a 2G at 2G direct-mapped window, and add
a Window 2 of 1G at 1G SGMAP-mapped.  Chain Window 2 to Window 1, and
use it as a fall-back for PCI DMA if the system has more than 2G of RAM.
 1999-04-15 23:47:52 +00:00
thorpej
31c4e50d3a - Change the "savunit[]" and "savirqs[]" arrays to ints, rather than chars. 
The access is more efficient this way (and this was done in the interrupt
  dispatch code, so some cycles are actually shaved), and gcc gets annoyed
  when chars are used as array subscripts.
- Adjust for the fixed Rawhide console initialization.
- When mapping a PCI interrupt, don't always map device 1 to IRQ 16.  Device
  1 is only the internal 53c810 on MID 5, and is an invalid device number
  on any other MID.
- Adjust for change mcpcia_config/mcpcia_softc structures.
- Nuke the kludgy linked list of mcpcia_softc structures.  Instead, just
  use savunit[v] to index into mcpcia_cd.cd_devs[] to find the MCPCIA
  which has the stray interrupt.
- Some other minor cosmetic cleanup.
 1999-04-15 22:37:25 +00:00
thorpej
592cdd4bda Adjust for new register access arguments, and make one slight cosmetic 
change.
 1999-04-15 22:32:21 +00:00