for modern PCI SATA controllers to have more. Define a new PCIIDE_MAX_CHANNELS
which to specify the maximum number of channels we support, and use it to
allocate channel resources.
register for proper operation. Add a prototype field in the pciide_channel
for this register and use it as necessary when writing the IDEDMA_CMD
register.
in a different fashion. Individually, they have the same functionality,
but their layout is different. An example of such a chipset is
the Promise 203xx.
To be able to deal with this, transform the cmd and dma bus_space handles
into an array of handles, each seperately created with bus_space_subregion.
The code generated by using the extra indirection shouldn't change much,
since the extra indirection is negated by having the offset calculation
already done in bus_space_subregion. E.g.
bus_space_write_4(tag, handle, offset, value)
becomes
bus_space_write_4(tag, handles[offset], 0, value)
Reviewed by Manuel Bouyer. Tested on wdc_isa, wdc_pcmcia, viaide, piixide (i386)
and on cmdide (sparc64).
http://mail-index.netbsd.org/tech-kern/2003/09/25/0007.html
We now have:
acardide* at pci? dev ? function ? # Acard IDE controllers
aceride* at pci? dev ? function ? # Acer Lab IDE controllers
cmdide* at pci? dev ? function ? # CMD tech IDE controllers
cypide* at pci? dev ? function ? # Cypress IDE controllers
hptide* at pci? dev ? function ? # Triones/HighPoint IDE controllers
optiide* at pci? dev ? function ? # Opti IDE controllers
piixide* at pci? dev ? function ? # Intel IDE controllers
pdcide* at pci? dev ? function ? # Promise IDE controllers
siside* at pci? dev ? function ? # SiS IDE controllers
slide* at pci? dev ? function ? # Symphony Labs IDE controllers
viaide* at pci? dev ? function ? # VIA/AMD/Nvidia IDE controllers
pciide* at pci? dev ? function ? flags 0x0000 # GENERIC pciide driver
serverworks driver not commited yet; there are still copyright issues about
it.
IDE controllers, which are more-or-less compatible with the
AMD controllers.
XXX Need to determine the correct timing value for the nForce2
XXX at Ultra133, so we cap it at Ultra100, for now.
them define __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH
in pci_machdep.h and pciide_map_compat_intr() only calls
pciide_machdep_compat_intr_establish() if that preprocessor
define exists.
Ports that don't need to do this no longer need to supply a
dummy function.
Paul Kranenburg, many thanks !): the control register I/O is 4 byte long
although only one is used, but the control register is at offset 2, and not
0 as expected by IC code. Use bus_space_subregion() to get a handle which
points to the control register, and is one byte long.
if an IRQ was not detected, unless the force flag was given. Use this to
detect if the IRQ was for us (closer to shared IRQ for controllers which
don't have their own IRQ handler in pciide.c) and to poll for DMA xfer.
Also makes the timeout recovery code simpler.
- ATAPI cleanup: don't call controller-specific functions from atapiconf.c
(wdc_*), so that it's possible to attach an atapibus to something else
than a wdc/pciide (Hi Lennart :).
Overload struct scsi_adapter with struct atapi_adapter, defined
as struct scsi_adapter + atapi-specific callbacks. scsipi_link still points
to an scsi_adapter, atapi code casts it to atapi_adapter if needed.
Move atapi_softc to atapiconf.h so that it can be used by the underlying
controller code (e.g. atapi_wdc.c).
Add an atapi-specific callback *atapi_probedev(), which probe a drive
in a controller-specific way, allocate the sc_link and fills in the
ataparams if needed. It then calls atapi_probedev() (from atapiconf.c)
to do the generic initialisations and attach the device.
- While I'm there merge and centralise the state definitions in atavar.h.
It should now be possible to use a common ata/atapi routine to set the
drive's modes (will do later).
