- Allocate interrupt handles dynamically from a pool(9) to reduce the
number of TLB misses during interrupt dispatch.
- Fully support evcnt(9) in all interrupt dispatchers.
- sysfpga_sreset()
Hit the soft-reset register to reset the board.
- sysfpga_twinkle_led()
Might as well put the blinkenlight on the Cayman to good use as
a "heartbeat" indicator.
should have been bus_space_write_stream_2().
The sm(4) driver gets a bit further now.
While I'm here, g/c a debug printf accidentally commited last time around.
The latter's probe doesn't pick up the ethernet controller, and the
attach function needs to set MIIF_NOISOLATE.
We attach it at superio mainly because they share the same region of
address space, and the ethernet controller's interrupt is routed
through the superio.
SH-5, meet NetBSD.
Let's hope this is the start of a long and fruitful relationship. :-)
This code, funded by Wasabi Systems, adds initial support for the
Hitachi SuperH(tm) SH-5 cpu architecture to NetBSD.
At the present time, NetBSD/evbsh5 only runs on a SH-5 core simulator
which has no simulated devices other than a simple console. However, it
is good enough to get to the "root device: " prompt.
Device driver support for Real SH-5 Hardware is in place, particularly for
supporting the up-coming Cayman evaluation board, and should be quite
easy to get running when the hardware is available.
There is no in-tree toolchain for this port at this time. Gcc-current has
rudimentary SH-5 support but it is known to be buggy. A working toolchain
was obtained from SuperH to facilitate this port. Gcc-current will be
fixed in due course.
The SH-5 architecture is fully 64-bit capable, although NetBSD/evbsh5 has
currently only been tested in 32-bit mode. It is bi-endian, via a boot-
time option and it also has an "SHcompact" mode in which it will execute
SH-[34] user-land instructions.
For more information on the SH-5, see www.superh.com. Suffice to say it
is *not* just another respin of the SH-[34].
