Commit Graph

2805 Commits

Author SHA1 Message Date
simonb
9d7facdb6e Yanking a pmax-specific header should not have broken Alpha
compiles!  Remove all pmax include files, copying 'struct pdma'
from <pmax/dev/pdma.h> into sccvar.h.

XXX: diffs between current pmax and alpha scc.c are almost as large
     as the files themselves.  Should clean this up...
2001-08-26 16:39:56 +00:00
nisimura
4d28b238b5 Add MX (PMAG-A) and TX (PMAG-RO/PMAG[B]-J) supports and replace CX
(PMAG-B) code with one found in dev/tc/ directory.
2001-08-23 01:29:31 +00:00
nisimura
9a409cff3e Add MX (PMAG-A), CX (PMAG-B), TX (PMAG-RO/PMAG[B]-J) TC framebuffer
supports.  None of them has any acceleration capability.
2001-08-23 01:16:52 +00:00
hubertf
5366e197e2 More comment changes: 90x[B] -> 90x[BC] 2001-08-22 15:39:04 +00:00
wiz
c52d355d71 "wierd" is weird. 2001-08-20 12:20:01 +00:00
mrg
dc4e692845 add a commented "options NETATALK" 2001-08-20 04:49:17 +00:00
chs
3f98593d27 in vunmapbuf(), call pmap_*remove() explicitly since uvm_km_free_wakeup()
will soon no longer do it for us.
2001-08-19 17:34:01 +00:00
mjacob
7a43c0e46b Fixed the one minor buglet that kept 8200s from working
(SCB_VECTOIDX(vec) - SCB_IOVECBASE] -> SCB_VECTOIDX(vec - SCB_IOVECBASE))

Sigh. This is all very good work- this new interrupt stuff. Yet like the
last time my good friend Jason 'simplified' things, we lost information.
It used to be you could tell which specific slot an interrupt was frame
based upon the vector. Now you can't because they're allocated dynamically.
Oh well- it's not all that important.
2001-08-13 23:36:30 +00:00
chs
610af327b3 add an unlock missing from previous revision. 2001-08-13 01:12:15 +00:00
jdolecek
c495131fe3 Move _insque()/_remque() to libkern. Once remaining uses would
be converted to <sys/queue.h> macros, _insque()/_remque() would be eliminated
altogether.
2001-08-12 08:35:31 +00:00
bjh21
ad2c12a28d Bump version numbers of all bootloaders that use loadfile/ELF, to account for
my changes to symbol loading.  I should probably have done this at the time,
but it's better late than never.
2001-08-02 12:24:05 +00:00
thorpej
0fb6b9a8f8 Rework the interrupt code, shaving some cycles off in the process.
Rather than an "iointr" routine that decomposes a vector into an
IRQ, we maintain a vector table directly, hooking up each "iointr"
routine at the correct vector.  This also allows us to hook device
interrupts up to specific vectors (c.f. Jensen).

We can shave even more cycles off, here, and I will, but it requires
some changes to the alpha_shared_intr stuff.
2001-07-27 00:25:18 +00:00
wiz
684d06bac8 bcopy -> memcpy, bzero -> memset 2001-07-22 15:17:30 +00:00
wiz
a9356936b4 seperate -> separate 2001-07-22 13:33:58 +00:00
thorpej
030941bc0d Only match the "gbus" on the primary CPU's CPU module. 2001-07-19 20:34:08 +00:00
thorpej
13e63c6a43 Take a guess and initialize the prefetch threshold to 256 bytes. Haven't
found this one in the manual yet.
2001-07-19 19:09:22 +00:00
thorpej
b0256ef005 DWLPx has a 256-byte DMA prefetch threshold. 2001-07-19 18:59:41 +00:00
thorpej
1e21ada1d9 MCPCIA has a 256 byte DMA prefetch threshold. 2001-07-19 18:55:40 +00:00
thorpej
c563df226b The T2 has a 256 byte DMA prefetch threshold. 2001-07-19 18:50:25 +00:00
thorpej
e6ab362da0 The LCA isn't supposed to have a DMA prefetch threshold, but experience
has shown is that if we don't allocate a spill page, we get a machine
check.  So, initialize the threshold to 256 bytes.
2001-07-19 18:47:38 +00:00
thorpej
4c4c88dbb7 ALCOR/ALCOR2/PYXIS have a 256-byte DMA prefetch threshold. 2001-07-19 18:42:42 +00:00
thorpej
908464bef9 APECS has a 256 byte DMA prefetch threshold. 2001-07-19 18:39:29 +00:00
thorpej
63bc6c1370 Since the SGMAP buffer load subroutine doesn't need to modify
the segment index, don't pass it by reference.
2001-07-19 18:20:20 +00:00
thorpej
77e1f86ad4 Implement dmamap_load_uio for SGMAPs. 2001-07-19 18:08:54 +00:00
thorpej
e60fffea3b Pay attention to BUS_DMA_READ; don't need to allocate a spill
page if it is set.
2001-07-19 17:08:44 +00:00
thorpej
babefc5331 Add BUS_DMA_READ and BUS_DMA_WRITE flags, that hint the back-end
at dmamap load time that the mapping will be used for a unidirectional
transfer of the specified direction.
2001-07-19 15:32:10 +00:00
thorpej
b70733d358 Since DMA frobbing can be done at interrupt time by devies at
multiple levels, protect the extent map w/ splvm().
2001-07-19 14:26:54 +00:00
thorpej
18490eff62 Add support for mbufs to the Alpha SGMAP DMA maps. 2001-07-19 06:40:01 +00:00
thorpej
8617f2c7f5 Simplify the SGMAP code a bit, and move SGVA allocation out of a
common routine into the individual load routines, since each load
routine needs to muddle with the "internals" of this operation.

Add a `prefetch threshold' member to the bus_dma_tag_t, so that
eventually we can determine whether or not to allocate a spill
page on a per-mapping basis.
2001-07-19 04:27:37 +00:00
thorpej
09ab6c5da8 Duh, to set the user stack pointer, you have to frob the PALcode PCB,
not the trap frame.

Fixes clone(2) on the Alpha.
2001-07-18 22:22:49 +00:00
thorpej
6af9e1cf38 Print the stack pointer on a user unaligned access fault. 2001-07-18 22:22:02 +00:00
thorpej
909084d90f Protect userland from the inlines and kernel variable decls. 2001-07-17 20:54:58 +00:00
thorpej
3e1e8af07b Don't use pmap_changebit() in pmap_protect(), and remove the
pager mapping check from pmap_changebit().
2001-07-16 21:37:21 +00:00
thorpej
aff311a28c Remove I-sync stuff from pmap_changebit(). The AARM says that we
only have to sync the I-stream when the mapping is removed or chaged,
and since the I-stream is fetch-only, changing protection bits does
not constitute changing the mapping (the VA->PA translation is still
the same).
2001-07-16 19:48:03 +00:00
elric
99e8b114e0 So, the PowerStorm 4d20 a.k.a. 32bit TGA2 w/ IBM RGB561 RAMDAC was causing
the kernel to panic since it is recognised as a TGA and the TGA driver
doesn't [yet] know what to do with it.

This patch fixes that by:
	o  making tgamatch() try to actually figure out what kind
	   of TGA card is there, rather than simply relying on the
	   vendor/product ids.
	o  creating a tga_cnmatch() so that the console code in
	   arch/alpha/pci/pci_machdep.c can cause the same to occur.
	o  breaking up some of tga_getdevconfig() into a few different
	   functions to re-use code that would have been duplicated.
	o  changed arch/alpha/pci/pci_machdep.c so that it calls out
	   to tga_cnmatch() if DEVICE_IS_TGA() matches before it decides
	   to attach the console as a TGA.

Addresses PR: port-alpha/12923
2001-07-16 00:55:16 +00:00
thorpej
dcfd225d73 Defer sending shootdown IPIs a bit longer. Reduces traffic a fair
bit more.
2001-07-15 21:57:01 +00:00
thorpej
ff62d4c0c5 - Tweak the pmap locking protocol slightly -- require that a pmap must
be locked before it can be marked as `active' on a processor.
- Require that pmaps other than the kernel pmap be locked when they
  are passed to pmap_tlb_shootdown().  This, combined with the locking
  protocol tweak, allow us to get a consistent view of `activeness' of
  a pmap, which means we can optmize away a lot of TLB shootdown traffic
  for user pmaps.
- Borrow an idea from the i386mp branch; use the normal SHOOTDOWN IPI
  to deal with hitting the entire TLB, and garbage-collect the TBIA
  and TBIAP IPIs.
2001-07-15 16:42:18 +00:00
thorpej
f79117f725 UVM never passes us a NULL pmap argument; remove that Mach VM leftover. 2001-07-15 05:24:20 +00:00
thorpej
6908e679ac Cosmetic change. 2001-07-14 17:55:42 +00:00
thorpej
3eeb00e998 Oops, only register those event counters if the primary processor. 2001-07-14 05:48:45 +00:00
thorpej
c022450f9c Instrument the lazy FP context switch path:
- fpevent_use is incremented the first time a process uses FP
  for the first time (note, FPUSED is inherited on fork, but
  cleared on exec).
- fpevent_reuse is incremented whenever a process that has previously
  used FP has to take a FEN trap in order to be able to use it again.
2001-07-14 05:10:38 +00:00
thorpej
335571bc61 Change the way we spin up CPUs. Now boot the CPU as soon as we
discover it, but make it block on a semaphore until the MI kernel
says that we can let the secondary processors loose.  This allows
us to announce the extensions on the secondary CPUs, and to compute
the intersection of all the extensions across all CPUs, like so:

cpu0 at mainbus0: ID 0 (primary), 21164A-2
cpu0: Architecture extensions: 1<BWX>
cpu1 at mainbus0: ID 1, 21164A-2
cpu1: Architecture extensions: 1<BWX>
2001-07-13 21:34:35 +00:00
thorpej
d819792e68 Use memcpy() in kcopy(), copyin(), and copyout(). XXX This means we have
to burn 3 insns to swap the arguments.  Need to change the interface to
these routines to match memcpy().

G/C bcopy() from here.  We'll let it be provided by libkern (which is
what provides memcpy()) until bcopy() is exorcised completely.
2001-07-13 00:06:06 +00:00
thorpej
97d7c635b0 bcopy -> memcpy 2001-07-12 23:35:42 +00:00
thorpej
1dd3ea59f6 bcmp -> memcmp 2001-07-12 23:26:30 +00:00
thorpej
294259060c bzero -> memset 2001-07-12 23:25:39 +00:00
soren
ce3293accb ncr(8) is gone from the tree, so remove ^#ncr*. 2001-07-09 15:05:22 +00:00
abs
01b024cd5b Standardise TCP_COMPAT_42 as commented out, grouped with other COMPAT options,
and with the comment '4.2BSD TCP/IP bug compat. Not recommended'
Add commented out 'TCP_DEBUG # Record last TCP_NDEBUG packets with SO_DEBUG'
(All hail amiga and atari which make some attempt to automate the
multiplicity of config files...)
2001-07-08 16:32:12 +00:00
tsutsui
df016928f8 Remove (commented out) ncr* at pci? lines. 2001-07-07 17:09:47 +00:00
toshii
4866f1a22b Fix typo. s/extention/extension/ 2001-07-05 08:38:24 +00:00