multiprocessor support:
- Implement MP-safe halt.
- Make the FPU saving code more like Bill's on the i386 MP branch.
XXX This code will no doubt be revisited again.
- Pass the cpu_info and trapframe to IPI handlers, saving some work
in the handlers themselves, and also making it possible for the
"pause" handler to reference register state for DDB.
- Add "machine cpu" to DDB, making it possible to reference other
CPUs registers (and thus get e.g. a traceback) from whichever
CPU is actually running the debugger.
- Garbage-collect "machine halt" and "machine reboot" DDB commands.
They don't have a prayer of working properly in multiprocessor
kernels, and didn't really work all that well in uniprocessor kernels.
- Add a bitmask for the CPUs which need an isync before this pmap returns
to userspace on that CPU.
- Define PMAP_USERRET(), a utility macro for userret() to use to process
the deferred isync, and call it as appropriate in userret().
longer need to lock the kernel pmap in pmap_kenter_pa() and pmap_kremove().
- Since locking the kernel pmap in interrupt context is no longer required,
don't go to splimp() when locking the kernel pmap.
- Implement a new pmap_remove() function, not yet enabled by default. It
is structured like pmap_protect, and should be *much* faster. This was
actually written quite some time ago, but never committed because it
didn't work properly. Given the recent bugfix to pmap_protect(), "duh,
of course it didn't work properly before...". It seems to work fine now
(have done several builds and run the UVM regression tests using the new
code), but it is currently run-time optional so that some performance
measurements can be easily run against the old and new code.
context, so we must block interrupts which may cause memory allocation
before asserting the kernel pmap's lock. Put this all in PMAP_LOCK()
and PMAP_UNLOCK() macros to make it easier.
UVM pmap's locking protocol, written by Chuck Cranor. Not all of the
support for multiple processors is here yet, but the kernel does run
under moderate loads with LOCKDEBUG (all locking operations are no-ops
unless LOCKDEBUG is turned on).
This is by no means complete... there are still some possible snares
to take a look at.
caller to pass an optional 3rd argument, which is the previous level
PTE corresponding the virtual address. If this argument is non-NULL,
the table walk otherwise necessary will be bypassed.
from the mach3 versions only as much as necessary to allow the old
NetBSD/Alpha pmap code to compile. THESE WILL NOT WORK AS-IS, and at
minimum will require code to implement reference- and modified-bit
emulation.
Support for AXPpci CPUs,
Support for AlphaStation 600 CPUs,
new boot block structure, which requires an 'installboot'
program and works a lot like the NetBSD/sparc boot blocks.
thorpej