- merged multiple DRQ/DTQ ADD macros into a single DRQ and a single DTQ
macro with a uniform interface to make the code simpler and easier to read.
- en_start: only update atm_flags if EN_MBUF_OPT is enabled (which it
should be)
- for alburst: make sure we don't DMA more bytes than we need (on both
tx and rx). if the alburst is larger than we need, drop to
MIDDMA_WORD mode.
- major change: enable the use of byte and 2 byte DMA on the trasmit side.
this allows us to DMA from non-word sized/aligned mbufs directly.
[the old code would always call en_mfix which would copy (or move) the
data in order to ensure proper alignment... it turns out TCP gives
us non-word sized/aligned mbufs when it is retransmitting, so we needed
to handle this case more efficiently.] the following functions
were changed to make this work:
- en_dqneed: add an arg to let us know if we are transmitting or not.
if we are TX, then we must take into account byte DMAs when
estimating the number of DTQs we will need for a buffer
- en_start: only mfix mbufs if DMA is disabled
- en_txdma: only set launch.nodma if we have en_mfix'd the mbuf chain
also, we may need a DTQ to flush the chip's internal byte buffer
- en_txlaunch: only attempt a copy if we have the proper alignment.
add byte dma code for the front and end of the buffer.
make sure the internal dma buffer is flushed out.
- stats: keep track of how many times we have to use byte sized DMA
midwayreg:
- add byte/2byte DMA defines
midwayvar:
- add new stat counter to monitor less-than-word lengthed DMA
[1] rxslot "cur" pointer wasn't updated if we copied all data and
didn't have any fill. this could cause a service id mismatch
panic under load.
[2] recv of aal0 forgot to include the cell header in the data length
calc [add cell header length to midwayreg.h]
[3] fix control info "chop" for raw mode and aal0
[4] handle rxsb better for native atm connections
(XXX: still working on this ... not complete and needs revision)
chuck