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986af15320
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62 Commits

Author SHA1 Message Date
scw
986af15320 Setup the IRL[0-3] mode according to what the kernel config file specifies. 2002-08-30 10:41:24 +00:00
scw
14b4efaf64 If running on the simulator, skip the pbridge probe. 2002-08-30 10:39:26 +00:00
scw
f8f7664ef6 Defflag/param some options for: 
- selecting Simulator/ST50 Debugger targets,
  - hard-coding the cpu speed instead of using the speed detection code,
  - changing the default kernel IPT size,
  - selecting the IRL[0-3] mode to configure in the interrupt controller.
 2002-08-30 10:29:35 +00:00
scw
1256340461 Add the frame pointer (r14) to the list of registers to save in 
the pcb during a context switch.
 2002-08-29 16:04:10 +00:00
scw
9af86f9bf3 Oops, got the source operands for an "andc" reversed. 
This gets the hardware interrupt event handler working.
 2002-08-28 21:05:25 +00:00
scw
f6e3925495 Set the appropriate Timer Start bit after setting it all up. 2002-08-26 10:48:17 +00:00
scw
aba39b410c Don't forget to initialise 'sc' on entry to the attach function ... 2002-08-26 10:45:55 +00:00
scw
a1ed033a09 Hardcode FEMI base and top addresses, at least until I figure out 
how to interpet VCR.MB_TOP and VCR.MB_BOT in some reasonable way.
 2002-08-26 10:43:44 +00:00
scw
3ad3b8c856 Add MD ddb(4) files. 2002-08-26 10:39:43 +00:00
scw
a57d38854c Save SSR and SPC while in the critical section of an exception. The 
previous behaviour of storing them with SR.BL clear was in breach
of the SH5 documentation.

Make an effort to catch PANIC traps and dump machine state to the console.
 2002-08-26 10:38:52 +00:00
scw
40f78dcc13 Use pmap_map_device() to map device registers. 2002-08-26 10:35:40 +00:00
scw
8bd3eb387d Don't block exceptions in the initial SR value. 2002-08-26 10:34:43 +00:00
scw
10ce1fc51b s/pmap_bootstrap_mapping/pmap_map_device/ 2002-08-26 10:33:33 +00:00
scw
abc568b5e1 In cpu_fork(), if p1 == curproc, call sh5_savectx() to ensure the 
pcb contains valid state before copying it to p2's pcb.
Previously, we just lazy-sync the fpu state. This wasn't quite good
enough if p1 had not previously slept.
 2002-08-26 10:32:55 +00:00
scw
0a00df79a0 Initialise to zero the memory allocated for interrupt handles. 2002-08-26 10:26:28 +00:00
scw
d2c90421b8 Enable h/w interrupts before returning from cpu_configure(). 2002-08-26 10:24:57 +00:00
scw
bc8042954a - Add a debug check for SR.BL being set on entry to cpu_switch(). 
- Add sh5_savectx()
- Fix a branch target register botch in sh5_fpsave() and sh5_fprestore().
 2002-08-26 10:23:56 +00:00
scw
7bd8b94a66 Wrap dump_kipt() in #ifdef DDB. 2002-08-26 10:21:54 +00:00
scw
d8f6a57b15 Re-work pmap_bootstrap_mapping() to pmap_map_device() to provide a 
way for bus_space(9) to efficiently map device memory. (Although at
the moment, it doesn't quite work as efficiently as it will down
the line ...)

Fix a pool_init() botch.

Add a debug aid: dump_kipt(). This can be called from ddb(4) in order
to (partially) dump the contents of the kernel IPT.
 2002-08-26 10:21:04 +00:00
scw
2774f9d77b Basic ddb(4) support. 
Still to do:
 - disassembly
 - breakpoints
 - single-step
 - stack trace
 2002-08-26 10:16:44 +00:00
scw
16ba45622a - Drop to ddb(4) on kernel traps. 
- Dump more machine state on kernel traps (for when ddb isn't an option).
- Add rudimentary support for PANIC exceptions.
 2002-08-26 10:14:02 +00:00
scw
d454acf190 Disable the checks for unsupported hz values for now. At least until I 
can fix the peripheral bridge's PLL1 clock ratio.
 2002-08-26 10:10:22 +00:00
scw
b5273356dc - Invalidate insn/operand caches before setting up the mmu for the first time. 
- Clear SR.FD to enable the FPU. Seems like it starts up disabled. If the
  core has no FPU, this is a nop.

- Preserve the debug bits (step/watch) in an attempt to appease the debugger.
 2002-08-26 10:08:02 +00:00
scw
911776caaf Impose a limit on the time we spin waiting for the DTF host to ack 
our packet. Seems like the ack for the initial posix console "open"
packet never arrives, even though it completes successfully.
 2002-08-26 10:04:05 +00:00
briggs
0b956d0b8b Implement pmc(9) -- An interface to hardware performance monitoring 
counters.  These counters do not exist on all CPUs, but where they
do exist, can be used for counting events such as dcache misses that
would otherwise be difficult or impossible to instrument by code
inspection or hardware simulation.

pmc(9) is meant to be a general interface.  Initially, the Intel XScale
counters are the only ones supported.
 2002-08-07 05:14:47 +00:00
scw
a486314d8a Apply thorpej's recent All-Ports conf.c change. Seems SH5 slipped 
through the net the first time around. Here's the relevant snippet
of the original commit message:

Rename cdev_systrace_init() to cdev_clonemisc_init(), so it can
be properly used by any misc. cloning device.
 2002-07-19 18:53:15 +00:00
scw
d911ae5d57 SH5 systrace(5) glue. 2002-07-12 20:43:12 +00:00
scw
6daca7f652 Ditch the "simulated clock" hack. It would never really have worked, 
and the latest simulator won't need it anyway.
 2002-07-12 19:52:21 +00:00
scw
e9688612da Make it so kernels can be compiled for 32-bit or 64-bit with a 
simple config file option.

Also, don't hard code the endian setting in a header file. Rely instead
on the compiler defining __LITTLE_ENDIAN__ and DTRT as appropriate.
 2002-07-12 19:33:27 +00:00
scw
3a5b311011 Cast a pointer to uintptr_t before comparing with a long int. 2002-07-12 19:27:32 +00:00
scw
c02c1c7cd2 Clean up <sh5/asm.h> to be more 64-bit friendly. 
Clean up the kernel asm files to be less 32-bit dependent.
 2002-07-12 15:42:27 +00:00
scw
1664941b2c Blah, missed a comma. 2002-07-12 13:37:32 +00:00
scw
2675306718 Add IEEE FP mode control functions and definitions for SH5. 2002-07-12 12:20:24 +00:00
scw
67ea1085eb Add MD procfs stub for SH5. 2002-07-12 11:20:12 +00:00
scw
270555326f More SH5 toolchain hacks: Don't define _BSD_WCHAR_T if compiling C++. 2002-07-12 11:19:08 +00:00
scw
60fb656ee5 Validate the branch target registers and saved PC using the 
appropriate macro.
 2002-07-11 21:23:30 +00:00
scw
14013f679d Add a macro which verifies that a 64-bit value is a valid effective 
address as defined by the cpu's Implemented Effective Address bits.
 2002-07-11 21:21:58 +00:00
scw
d08670adc8 Sync with reality. 2002-07-11 21:20:23 +00:00
scw
0d0a6374ef Some cleanups for the MACHINE_ARCH endian suffix change. 2002-07-11 14:42:55 +00:00
scw
d55184012a Cleanup the sigcontext structure, and sync {,sig}jmp_buf size and 
offsets with it.
 2002-07-11 14:16:42 +00:00
scw
5c90e3c0d6 In sys___sigreturn14(), validate the saved branch target registers and 
program counter to avoid a possible kernel-mode IADDERR exception when
we try to restore the trapframe on return to user-mode.
 2002-07-11 14:15:32 +00:00
scw
384b76c19b Install <sh5/pte.h> for the benefit of cpu.h. 2002-07-11 14:11:18 +00:00
scw
e0e8310758 Include <machine/frame.h>, not <sh5/frame.h> 2002-07-11 14:10:39 +00:00
scw
026df6bf33 Cleanup the frame link/unlink macroes. 2002-07-11 14:09:34 +00:00
scw
b234c1aa10 Moved MID_MACHINE definition from <machine/param.h> 2002-07-11 14:08:45 +00:00
scw
52876ee77d First cut of the kernel side support for sh5 signals. 2002-07-10 15:55:01 +00:00
scw
528a743ee9 Update sh5_fpsave() prototype to match reality. 2002-07-10 15:53:57 +00:00
scw
a30ba3dd9a Need <sys/types.h> 2002-07-10 15:52:49 +00:00
scw
f78244feaf Before returning to userland, clear the FPU regs saved flag. 2002-07-10 15:52:07 +00:00
scw
0f3678d589 Track FPU register save status. 2002-07-10 15:49:33 +00:00