since BTLB entries can be scarce and very little of an I/O subsystem normally
needs to be mapped.
Instead, the pmap now allows mappings of I/O space to be entered with
pmap_kenter_pa. bus_space mappings for small amounts of I/O space (as for
virtually all devices) are made this way, with BTLB entries still used for
large mappings for things like framebuffers.
This has led to more and cleaned-up uses of bus_space(9) and has caused
some autoconf cleanup. Also, kgdb is now attached and connected before
autoconfiguration, which is much earlier than before.
in struct hppa_cpu_info or anywhere else, now there are just hppa_btlb_*
functions. Added support for machines with split I/D and variable-range
BTLBs. Added support for purging BTLB entries.
they contain. IRQ information for these has been removed from the
kernel configuration file. GSC bus chips now choose an available CPU
IRQ for themselves, and know IRQ information for all of the devices
they may contain. Minor autoconfiguration changes support this.
Renamed the old-style vmstat interrupt counters to say "ipl" and not
"irq", since they've been disconnected from irq numbers. Also provide
a function to allocate an irq bit from an interrupt register, and a
function to report the next ipl bit that will be allocated.
longer a forced correspondence between bit numbers in an interrupt
register and bit numbers in an spl mask. This will avoid conflicts
between various interrupt registers in the same system.
Instead, bits in the spl mask are allocated on a first come, first
served basis by devices which can interrupt. The new hp700_intr_ipending_new
takes care of reading all interrupt request registers that need
servicing, and mapping the bits set in those registers to new bits
set in ipending.
This whole mechanism is in and works. A later commit will see the
I/O subsystems fixing which bits in their interrupt registers are
connected to which devices, largely removing irq information from
kernel configuration files. There will also be a cosmetic fix to
show which spl bit corresponds to a device.
to deal with aliasing of regular memory pages, because many processors don't
support it.
Now, the pmap marks all mappings of a page that has any non-equivalent
aliasing and any writable mapping, and the fault handlers watch for this
and flush other mappings out of the TLB and cache before (re)entering a
conflicting mapping.
When a page has non-equivalent aliasing, only one writable mapping at
a time may be in the TLB and cache. If no writable mapping is in the
TLB and cache, any number of read-only mappings may be.
The PA7100LC/PA7300LC fault handlers have not been converted yet.
counters. These counters do not exist on all CPUs, but where they
do exist, can be used for counting events such as dcache misses that
would otherwise be difficult or impossible to instrument by code
inspection or hardware simulation.
pmc(9) is meant to be a general interface. Initially, the Intel XScale
counters are the only ones supported.
maps it with BTLB entries, to minimize the number of BTLB entries
needed.
Because the CPU type was often guessed incorrectly, the mapping of
HP board number to system name now includes information about the
expected CPU type.
