Commit Graph

7 Commits

Author SHA1 Message Date
kent cd7d9faeaf Introduce BUS_DMA_NOCACHE, and bus_dmamem_map() of i386 supports it. 2003-01-28 01:07:51 +00:00
simonb a85e214bda Make sure that private DMA flags don't overlap with standard DMA flags;
start these at 0x10000 to leave room for an increase in the latter.
2002-03-17 21:45:06 +00:00
thorpej af66038f73 Merge the thorpej-mips-cache branch onto the trunk. This is an
overhaul of how caches are handled for NetBSD's MIPS ports.
2001-11-14 18:15:10 +00:00
thorpej 81bcece4d4 Implement bus_space_mmap(). 2001-09-04 16:32:42 +00:00
thorpej babefc5331 Add BUS_DMA_READ and BUS_DMA_WRITE flags, that hint the back-end
at dmamap load time that the mapping will be used for a unidirectional
transfer of the specified direction.
2001-07-19 15:32:10 +00:00
enami 299159546d s/Alpha/MIPS/ in comment. 2001-05-31 02:20:55 +00:00
thorpej 16b9c60621 A port to the Algorithmics MIPS evaluation boards. We currently
support the P-5064, which has a QED RM5xxx CPU soldered on.

There is some skeletal support for the P-4032 (an older board, which
had an R4xxx CPU).  There are some placeholders for the P-6032, which
is their newest board, but no real code yet (the P-6032 has a different
PCI controller, the Algorithmics BONITO).

There are still some (apprently softintr-related) problems with the
algor kernel, but it works well-enough to self-host.

Kudos to Allegro Networks for loaning me a P-5064 board on which to do
the port.
2001-05-28 16:22:13 +00:00