* Support for the new softint mechanism. Softints are now requested by
triggering an unused ICU hardware interrupt. The idea for this was
contributed by Phil Budne.
* Real probe code added.
* Duart info is now allocated only for devices that are present.
* Added IO-Recovery delays for 30mhz systems.
* Removed a few potential NULL-pointer references.
>One control block per target is insufficient if you have a full complement
>of targets attached and access those simultaneously (like in a ccd(4) array).
>We (now) allocate (somewhat arbitrarily) three per target.
>Noticed by Marshall Midden.
don't machine check when a PCI Master Abort is signalled. This can
happen, for instance, when configuration space for a device that isn't
present is examined. When this is detected, act like we normally would
when machine checks are posted while examining nonexistant devices.
enabled (from the attach routine), and add comments as to why.
Some PALcode apparently 'saves' a clock interrupt for the kernel,
and if the clock interrupt handler is enabled at attach time, it
will be run when that interrupt hits, i.e. right after the spl0()
at the end of autoconfiguration. That would cause hardclock to be
run, but proc0's p_stats isn't set up by then, which would cause
hardclock to crash.
rather than and-ing 16G-1. That just strips the k0seg bits, rather
than making the false assumption that the physical address is going
to be in the lower 16G. That doesn't apply for CIA device-space
addresses, for instance.
even if PCI and the IDs are right), just for sanity, before declaring
success. Split the single 0x3b0 -> 0x3df allocation into three seperate
ones: 0x3b0 -> 0x3bc (leaving the 4 ports available for lpt),
0x3c0 -> 0x3cf, and 0x3d0 -> 0x3df. The former chunk has to be split
off if the lpt can exist there, and it's sort-of pretty to have each
group (based on second hex digit) have its own handle.
These alternative macros have a workaround for the STM^ bug in revision < 3
StrongARM CPU's that causes incorrect register saving if a cache line fill
is in progress during the STM.
a podulebus.
Make sure the podulebus driver conforms to the Acorn expansion card
specification:
- Probe the podule bus using sync access cycles rather than slow access
cycles.
- Read the podulebus header/ROM using sync access cycles rather than slow
access cycles
of targets attached and access those simultaneously (like in a ccd(4) array).
We (now) allocate (somewhat arbitrarily) three per target.
Noticed by Marshall Midden.
