Commit Graph

7 Commits

Author SHA1 Message Date
bjh21
cb5273b547 First attempt at an EtherH driver. Can just about transmit and receive
packets.  Interrupt enabling is left to the RISC OS driver, medium selection
is untested and it's hard-wired to the MAC address of my card.  Not really
for production use.
2000-12-01 14:28:36 +00:00
bjh21
40aba7cd4d Split the arm26 Ether3 (ea) driver into an MI driver for the SEEQ 8005 chip,
and a front-end driver for the Ether3.  Only semantic change is to remove
ea_claimirq() and ea_releaseirq() on the grounds that the seem too spurious
to warrant a callback to the front-end.
2000-09-18 20:51:14 +00:00
bjh21
41b1cb9327 Remove mention of truly dead files 2000-09-18 20:08:43 +00:00
bjh21
567f2768d1 Implement the easy ptrace requests and turn off the difficult ones. 2000-08-20 15:16:49 +00:00
bjh21
d7eebd9227 Basic driver for CHIPS 82C710 Universal Peripheral Controller and friends,
as used on later arm26 system (A5000, A4, A3010, A3020, A4000).

What we have got:
...
upc0 at iobus0 base 0x010000: config state bb 87 1c 00 00
fdc at upc0 offset 0x3f4 not configured
wdc0 at upc0 offset 0x1f0
lpt0 at upc0 offset 0x278
com0 at upc0 offset 0x3f8: ns8250 or ns16450, no fifo
...

What we haven't got:
 - FDC support (found, but not configured).
 - Clearing lpt interrupts on arm26 systems (needs help from IOEB).
 - A upc(4) manual page.
 - More than minimal testing (my A3020s don't have root devices).
 - A proper probe routine (arm26 can't use one anyway).
2000-08-16 23:56:08 +00:00
bjh21
4014c03b26 Replace copyinstr, copyoutstr and copystr with slightly more sensible
assembler versions.
2000-08-13 12:31:26 +00:00
bjh21
6c97e2bd78 Initial commit of arm26 port 2000-05-09 21:55:44 +00:00