pmap_copy_page, and pmap_clear_modify (pmap_clear_bit). Remove #ifdef
MULTIPROCESSOR since the cache instructions operate on all caches on
all processors.
* Byte-swap 16-bit and 32-bit constants at compile-time.
* Inline 16-bit and 32-bit variable byte-swaps. These take 3 and 4
insns, respectively, and inlining saves the minimum 6 cycle penalty
to call/return from the byte swap function.
common across many of the 4xx parts. Leaves ibm405gp.h with device
address information specific to the 405GP CPU. Now allows opb.c to
support multiple 4xx CPU types.
cache line allocation policy on XScale CPUs: in pmap_enter(), if the
pmap is the kernel pmap, clear the X-bit in the PTE, thus disabling
read/write-allocate for managed kernel mappings.
Yes, this is ugly. But it makes userland code run with r/w-allocate,
which is a huge improvement on systems with low core memory performance.
via the Configuration Port, so restructure the code a little
to allow for them, and list at least one other system that does
(anything based on AMD Elan SC520).
XXX We don't actually check for Elan SC520 yet.
documentation:
- Remove "mainbus" altogether.
- The new root is "plb" - the Processor Local Bus.
- Attached to this is the "opb" - the On-chip Peripheral Bus, to which
all the on-chip devices are attached (except the cpu and pci host
bridge).
- Port-specific code can pass an array of 'struct plb_dev' to
config_rootfound() to attach extra devices to the plb. The walnut
port attaches a "pbus" (Peripheral Bus) in here for the RTC and
pc keyboard controller to attach to.
There is still much 405GP specific code; the next round of changes will
generalise this to enable easier support for other 4xx CPUs.
driver attaches where "pchb" would normally attach (it matches at a
higher match priority). The "elansc" driver currently provides support
for the watchdog timer built-in the SC520.
Thanks to Jasper Wallace for laying the ground-work for this (most
notably by providing a work-around for a watchdog-related bug in the
SC520).
to deal with aliasing of regular memory pages, because many processors don't
support it.
Now, the pmap marks all mappings of a page that has any non-equivalent
aliasing and any writable mapping, and the fault handlers watch for this
and flush other mappings out of the TLB and cache before (re)entering a
conflicting mapping.
When a page has non-equivalent aliasing, only one writable mapping at
a time may be in the TLB and cache. If no writable mapping is in the
TLB and cache, any number of read-only mappings may be.
The PA7100LC/PA7300LC fault handlers have not been converted yet.
This version works on both 26-bit and 32-bit machines. For large copies,
it's up to three times as fast as the old arm32 version and five times as
fast as the old arm26 version. For small copies it seems to be even faster
(getrusage() is apparently over ten times faster on an ARM610).
Hooray for Allen!
