1. ifdef out the restriction that the SiS 900 has only one PHY
This is demonstrably false; the SiS 960 super south bridge in
PR 18590 has a SiS 900 rev 1 core in it.
2. bitbang the MII for all versions of the SiS 900; this is the
only way that the PHYs on this system answer.
Also, I suspect that SIS900_REV_960 constant in if_sipreg.h is
incorrectly labelled - there were later revisions of the super
south bridge (e.g. the 961, 962, and 963), and I suspect the
SiS 900 revision code there refers to one of those.
- Fix jumbo frame support.
- Disable interrupts at the chip in sip_intr().
- Disable checksum offloading if MTU > 8109 - the hardware is broken
in this case.
- Use the interrupt hold-off timer.
- Correct the Tx FIFO size.
- Add Pause Control/Status register definitions.
o Add support for the recent SiS96x chipsets that have a new revision.
That includes a new bit of code to access the EEPROM, since it is
shared with the ieee1394 controller on those chipsets.
Mostly taken from FreeBSD (rev. 1.62 and 1.64 of sys/pci/if_sip.c). I
tried to make the code look less ugly, but couldn't invent documentation.
Fix PR #23481. Thanks to Stephane ENGEL <sengel AT melshake DOT com> for
the report and the cheerful testing.
revisions have, as discussed on the soekris-tech mailing list a
while ago, whereby one can experience excessive recieve erros when
using < 30m cables. The patch detects overflow in a DSP filter
parameter, and corrects it by writing a known good value.
so that PHY instance is not siginificant in ifmedia_match(). This
is done to support multiple PHYs on the MII. Without this change,
ifmedia_set() would panic the system when no PHYs were matched.
I ran into this on an AMD EasyNow PC, which is built around SiS
system chips with an embedded SiS 900 core, and an external AMD
Am79c901 PHY, which presents two PHYs on the MII: one for HomePNA,
and one for standard 10base-T. The 10base-T PHY ends up with instance
number 1...
quirk table.
* We want to hardwire BMSR_EXTSTAT, not BMSR_EXTCAP, when reading
the TBI BMSR.
* Fetch the GPIO bits from the GPIOR register after an auto-load,
rather than reading from the EEPROM directly.
to enable 64-bit data transfers on 64-bit cards when plugged into
a 64-bit slot. Right know the Asante GigaNIX is listed in that
table.
Sigh, there is an EEPROM bit that can be used to detect 64-bit vs
32-bit cards. Unfortunately, at least 2 vendors of 32-bit cards
fail to clear the "DATA64_EN" bit in the EEPROM, which causes the
card to lose badly, because it still manages to detect that it's
plugged into a 64-bit PCI slot. Yay, stupid hardware vendors.
path: Instead of waiting for the if_snd queue to be drained before
giving ownership of the frist descriptor to the chip, do it after
sync'ing all the descriptors for a single packet.
* Get CFG_M64ADDR, CFG_T64ADDR, and CFG_DATA64_EN from the EEPROM.
Note, we still disable CFG_M64ADDR and CFG_T64ADDR later (XXX need
PCI bus capability flags for these).
* Print a message if we're in a 64-bit slot and 64-bit data is
disabled in the EEPROM. Make sure CFG_DATA64_EN is disabled if
we're not in a 64-bit slot.
- implement SIMPLEQ_REMOVE(head, elm, type, field). whilst it's O(n),
this mirrors the functionality of SLIST_REMOVE() (the other
singly-linked list type) and FreeBSD's STAILQ_REMOVE()
- remove the unnecessary elm arg from SIMPLEQ_REMOVE_HEAD().
this mirrors the functionality of SLIST_REMOVE_HEAD() (the other
singly-linked list type) and FreeBSD's STAILQ_REMOVE_HEAD()
- remove notes about SIMPLEQ not supporting arbitrary element removal
- use SIMPLEQ_FOREACH() instead of home-grown for loops
- use SIMPLEQ_EMPTY() appropriately
- use SIMPLEQ_*() instead of accessing sqh_first,sqh_last,sqe_next directly
- reorder manual page; be consistent about how the types are listed
- other minor cleanups
perry