This will allow improvements to the pmaps so that they can more easily defer expensive operations, eg tlb/cache flush, til the last possible moment.
Currently this is a no-op on most platforms, so they should see no difference.
Reviewed by Jason.
Thorpe as an extension to the bus_space(9) API.
Only the mainbus has a working mmap... iomd, podulebus and isa dont have
one yet. Its trivial to add the iomd and isa's memory part but am a bit
hessistant to add it without knowing its implications by heart.
Podulebus might be implemented in 32 bits EASI but otherwise its not really
transparent since there is AFAIK no function to explicitly read one byte or
so .. or is this implemented in a higher level ?
ARM26 and arch/arm32/dnard (Shark) kernels compile and RiscPC and Shark
kernels are tested and function OK.
Implications of other ARM systems like hpcarm and ebarm are propably
minimal or solved trivially.
Improved locking (not that we actually use it on a uniprocessor, but one day :)
Removed unneeded splvm's
tweaked pmap_clean_page code to only flush the cache if the page is mapped in the current pmap (based on diff from richard E)
Adopted pv entry allocation mechanism from i386.
Laid framework for returning ptp's when we've finished with them rather than holding onto them till the process exits.
ptp's are now allocated with a uvm object for the pmap, means that we can walk a list to free them off in pmap_release, until they get freed off by pmap_remove.
Also implemented a page zeroing function when the processor is idling. Note that hpcarm may wish to disable this.
I believe this code to be stable, if anyone has any problems please shout up.
bootable GENERAL kernel for the 3 machines.
This is done by integrating the ARM7500 in a better way. In various places
the IOMD ID is checked and action is taken at runtime compared to
compiletime.
The small piece of assembler that is changed now uses the flag
`arm7500_ioc_found' that is set up by iomd.c at startup. When this chip
isnt found at startup it will skip reading the ARM7500 extended IRQ
registers and wont clear them either.
The next step will be getting the mode-definition files to the bootloader.
Currently they are compiled in.
Note that I've some ideas in the works on how to improve the pv handling, so the slow down is short term only.
Also added non-advertising licence and copyright to myself and richard.
instruction that stores the program counter and the value of PC that's stored.
This can vary between ARM implementations, but is guaranteed to be constant on
a given one.
and late_abort_fixup(), based on the abort model in use, rather than the CPU
type. This cleans up the code and makes it smaller. Only tested on an
ARM6 -- I can't find my ARM710a card right now.
bjh21