NULL for root PCI busses. For busses behind a bridge, it points to
a persistent copy of the bridge's pcitag_t. This can be very useful
for machine-dependent PCI bus enumeration code.
* Implement a machine-dependent pci_enumerate_bus() for sparc64 which
uses OFW device nodes to enumerate the bus. When a PCI bus that is
behind a bridge is attached, pci_attach_hook() allocates a new PCI
chipset tag for the new bus and sets it's "curnode" to the OFW node
of the bridge. This is used as a starting point when enumerating
that bus. Root busses get the OFW node of the host bridge (psycho).
* Garbage-collect "ofpci" and "ofppb" from the sparc64 port.
* Pull in dev/mii/files.mii from conf/files, rather than playing
the magic "files include order" dance in N machine-dependent
configuration definitions.
after setting up the prom-based console. If more than one cpu class
is enabled, the wbflush() handler (needed indirectly by com.c) won't
be set up.
- Purge some old pmax mcclock-based code.
- Remove a '#if 1/#endif' pair.
- Use the CPU count register for more accurate microtime (from
sbmips) and delay (based on an evbmips delay function) functions.
- Schedule the next hardclock interrupt more accurately (from
an sgimips patch by Rafal Boni). Clock drift on one board is
now ~7ppm instead of ~330ppm.
- Purge old pmax-based mcclock code.
- Correctly round off some clock-derived variable calculations.
XXX: Some of this code should be migrated to sys/arch/mips.
become ippp (ISDN ppp) and irip (ISDN raw IP). The character device now
are called: /dev/isdn (isdnd <-> kernel communication), /dev/isdnctl (dialing
and other control), /dev/isdntrc* (tracing), /dev/isdnbchan* (raw B channel
access, i.e. for user land PPP) and /dev/isdntel* (telephone devices, i.e.
for answering machines).
MIPS32 4Kc CPU board, with support for the MIPS64 5Kc and the QED RM5261
CPU boards to follow.
The cs4281 audio hasn't been tested, there are some interrupt problems
with onboard the pciide, but all other on-board peripherals work.
The evbmips port will support more MIPS evaluation boards in the future.
christos