The irq delivery code has been rewritten. On entry to the irq vector the
processor is switched to SVC32 mode so all interrupt routines now run
in SVC32 mode rather than IRQ32 mode. This fixes lots of irq re-enabling
problems.
Interrupt latency times are now vastly improved for high priority interrupts.
Cleaned up calling ast() before returning to USR32 mode (don't need to
mess about with trapframe copying.
Cleaned up all the comments and sorted out their indentation.
Rewritten the soft interrupt delivery code.
Added generic ARM7500 support rather than just RC7500 support.
Fixed the handling of IPL_NONE.
Debugged support for interrupt chaining.
Fill out the intrnames array with the name of the interrupt handler
currently at the head of the chain.
Guarded several sanity checks with #ifdef DIAGNOSTIC.
irq_claim().
Clear the active flag in the irq handler when it is removed from the irq
chain in irq_release().
Checks for podule IRQ's in irq_claim() are now guarded with
#if NPODULEBUS > 0
fiq_release() now retrieves the FIQ more registers and places them
back in the fiq handler structure.
Remove the irq_setmasks() routine. This was coded in assembly months ago
and this C version is now out of date.
Added code for delivering IRQ_SOFTCLOCK.
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