- MP-safe drivers provide a mutex to ifmedia that is used to serialize
access to media-related structures / hardware regsiters. Converted
drivers use the new ifmedia_init_with_lock() function for this. The
new name is provided to ease the transition.
- Un-converted drivers continue to call ifmedia_init(), which will supply
a compatibility lock to be used instead. Several media-related entry
points must be aware of this compatibility lock, and are able to acquire
it recursively a limited number of times, if needed. This is a SPIN
mutex with priority IPL_NET.
- This same lock is used to serialize access to PHY registers and other
MII-related data structures.
The PHY drivers are modified to acquire and release the lock, as needed,
and assert the lock is held as a diagnostic aid.
The "usbnet" framework has had an overhaul of its internal locking
protocols to fit in with the media / mii changes, and the drivers adapted.
USB wifi drivers have been changed to provide their own adaptive mutex
to the ifmedia later via a new ieee80211_media_init_with_lock() function.
This is required because the USB drivers need an adaptive mutex.
Besised "usbnet", a few other drivers are converted: vmx, wm, ixgbe / ixv.
mcx also now calls ifmedia_init_with_lock() because it needs to also use
an adaptive mutex. The mcx driver still needs to be fully converted to
NET_MPSAFE.
Don't set the default value not in the attach function. Instead, set the
default value (MII_ANEGTICKS) first in the beginning of the
mii_phy_add_media(). The function already has the code to change the value to
MII_ANEGTICKS_GIGE if it's gigabit capable.
- Remove extra pmf_device_register() call. It's done in mii_phy_add_media().
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
This delay cause 500us loops under splnet() per linkdown port per mii_tick.
It causes periodically drop packets. It's not acceptable for other devices.
Move gphyter and nsphyter specific delay(500) into the drivers from
mii_physubr.c.
BMSR are wired to 0, yet the PHY supports 10baseT. So, to get around
this, we test the ANAR 10baseT bits after a PHY reset. These bits are
set according to input pin 180. If we see the 10baseT ANAR bits set,
we fake them in the BMSR so that we can actually autonegotiate 10baseT.
thorpej