int foo(struct lwp *l, void *v, register_t *retval)
to:
int foo(struct lwp *l, const struct foo_args *uap, register_t *retval)
Fixup compat code to not write into 'uap' and (in some cases) to actually
pass a correctly formatted 'uap' structure with the right name to the
next routine.
A few 'compat' routines that just call standard ones have been deleted.
All the 'compat' code compiles (along with the kernels required to test
build it).
98% done by automated scripts.
- Reduce available SPL levels for hardware devices to none, vm, sched, high.
- Acquire kernel_lock only for interrupts at IPL_VM.
- Implement threaded soft interrupts.
This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.
TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.
NOTES:
pmppc was removed as an arch, and moved to a evbppc target.
types. C99 requires that these definitions promote to (signed/unsigned)
integer the same way as the types the definition is for. And since
unsigned char/short fit into an "int" on all our archs and thus promote
to signed int, the definitions must not be unsigned.
Fixes PR lib/31306 by Neil Booth.
need to understand the locking around that field. Instead of setting
B_ERROR, set b_error instead. b_error is 'owned' by whoever completes
the I/O request.
link context instead of NULL. Otherwise, if we got a signal while the
lwp had a link context set, the link context would be set to NULL upon
return from signal delivery.
christos@tech-kern: "I think you are right."
meesing with the TLB. That would usually show up as misterious kernel
crashes under heavy load.
Prettify the code while here so that traversal of the memory mapped
TLB arrays looks congruent in all functions.
Fixes PR 34706
creating a trapframe, with exceptions disabled and using only BANK1
registers. If a valid pte is found, load it and return. Otherwise
create a trapframe and proceed to the full-blown C handler.
from doc/BRANCHES:
idle lwp, and some changes depending on it.
1. separate context switching and thread scheduling.
(cf. gmcgarry_ctxsw)
2. implement idle lwp.
3. clean up related MD/MI interfaces.
4. make scheduler(s) modular.
dsl