int values are added in DI (if the the constant is <0 & > -2*1024*1024 then
use a decl/subl and sbwc $0 instead of addl/adwc). The second fix is to
disallow register elimination peepholes when that register is used by
other operands in the other instructions in the peephole.
XXX if local address is specified in specific address family
(like IPv4 numeric addr) it will not be honored when we connect to different
address family (like IPv6 destination). there's no good way to circumvent this.
1999/08/02 Jakub Jelinek <jj@ultra.linux.cz>
* config/sparc/sparc.h (ASM_DECLARE_REGISTER_GLOBAL): New macro.
(RTX_OK_FOR_OLO10): Likewise.
(GO_IF_LEGITIMATE_ADDRESS): If assembler supports offsetable
%lo(), allow it in addresses...
(PRINT_OPERAND_ADDRESS): ... and print it appropriately.
* config/sparc/sparc.md (sethi_di_medlow_embmedany_pic): sethi %lo()
does not make sense.
* config/sparc/sparc.c (sparc_hard_reg_printed): New array.
(sparc_output_scratch_registers): New function.
(output_function_prologue, sparc_flat_output_function_prologue): Use
it.
* varasm.c (make_decl_rtl): Use ASM_DECLARE_REGISTER_GLOBAL if
defined.
* tm.texi (ASM_DECLARE_REGISTER_GLOBAL): Document it.
1999/07/30 Jakub Jelinek <jj@ultra.linux.cz>
* config/sparc/sparc.md (cmp_mul_set, cmp_udiv_cc_set):
Fix patterns so that they actually match.
(cmp_sdiv_cc_set): Ditto, also don't require g0 to be zero.
(mulsidi3_sp64, const_mulsidi3_sp64): New patterns.
(const_mulsidi3_sp32): Renamed from const_mulsidi3, only on
TARGET_HARD_MUL32.
(mulsidi3): Reflect this in the expand.
(smulsi3_highpart): Only on TARGET_ARCH32.
(umulsidi3_sp64, const_umulsidi3_sp64): New patterns.
(const_umulsidi3_sp32): Renamed from const_umulsidi3.
(umulsidi3): Reflect this in the expand.
(umulsi3_highpart): Only on TARGET_ARCH32.
(divsi3_sp32): Renamed from divsi3, only on TARGET_ARCH32,
don't require g0 to be zero.
(udivsi3_sp32): Renamed from udivsi3, only on TARGET_ARCH32.
({,u}divsi3): New expands.
({,u}divsi3_sp64): New patterns.
(after lshrdi3_v8plus): Four new patterns to help combiner
optimizing nested mixed mode shifts.
matt