to the L1 table and a virtual address, and no pointer to the L2 table.
The L2 table will be looked up by pmap_map_entry(), which will panic
if the there is no L2 table for the requested VA.
NOTE: IT IS EXTREMELY IMPORTANT THAT THE CORRECT VIRTUAL ADDRESS
BE PROVIDED TO pmap_map_entry()! Notably, the code that mapped
the kernel L2 tables into the kernel PT mapping L2 table were not
passing actual virtual addresses, but rather offsets into the range
mapped by the L2 table. I have fixed up all of these call sites,
and tested the resulting kernel on both an IQ80310 and a Shark.
Other portmasters should examine their pmap_map_entry() calls if
their new kernels fail.
Distinguish between 2312 and 2300 cards (they *are* different). Enable
RIO (Reduced Interrupt Operation) for the LVD cards (hey- I've seen
batched completions of the 30 commands at a time with this,....)...
If we get a Port Logout on local loop topologies, we have to force the
f/w to log back in. The easiest way (for us) to do this is to force
a LIP. This also will wake up the disk that probably just had a f/w crash.
Implement mailbox 'continuations'- this allows interrupts to re-drive
a mailbox command if it's one that just essentially repeats the previous
mailbox command (e.g., f/w download). This saves a boatload of sleep/wakeup
twitches.
If we're not a 2300 and we're about to return with a 'bogus interrupt'- check
the semaphore register to be non-zero at all and outgoing mailbox 0- this
seems to be where some of the lost ISP1080 commands came from.
and let pmap_map_chunk() lookup the correct one to use for the
current VA. Eliminate the "l2table" argument to pmap_map_chunk().
Add a second L2 table for mapping kernel text/data/bss on the
IQ80310 (fixes booting kernels with ramdisks).
header to distinguish between o32, n32 and n64 ABIs. We now use this.
This suppress the need of the mips_option test, which had some fake positive.
This also removes the mandatory ordering of n32 vs o32 in the exec switch
(exec_conf.c)
a byte-size quantity, the CacheLine Size configuration register specifies
the system cacheline size in units of 32-bit words; per PCI Local Bus
Specification, rev. 2.1, section 6.2.4.
kleink