Commit Graph

49 Commits

Author SHA1 Message Date
thorpej 0fb6b9a8f8 Rework the interrupt code, shaving some cycles off in the process.
Rather than an "iointr" routine that decomposes a vector into an
IRQ, we maintain a vector table directly, hooking up each "iointr"
routine at the correct vector.  This also allows us to hook device
interrupts up to specific vectors (c.f. Jensen).

We can shave even more cycles off, here, and I will, but it requires
some changes to the alpha_shared_intr stuff.
2001-07-27 00:25:18 +00:00
thorpej ff62d4c0c5 - Tweak the pmap locking protocol slightly -- require that a pmap must
be locked before it can be marked as `active' on a processor.
- Require that pmaps other than the kernel pmap be locked when they
  are passed to pmap_tlb_shootdown().  This, combined with the locking
  protocol tweak, allow us to get a consistent view of `activeness' of
  a pmap, which means we can optmize away a lot of TLB shootdown traffic
  for user pmaps.
- Borrow an idea from the i386mp branch; use the normal SHOOTDOWN IPI
  to deal with hitting the entire TLB, and garbage-collect the TBIA
  and TBIAP IPIs.
2001-07-15 16:42:18 +00:00
thorpej 53c1b3f9d7 Add a microtime() implementation that interpolates between ticks
using the cycle counter.  MP-safeness is achieved by giving each
CPU its own PCC frequency variables, and kicking the non-primary
processors via an IPI once per second.

Based on the sample code from David Mills' "A Kernel Model for
Precision Timekeeping".
2001-04-28 06:10:49 +00:00
thorpej b8ccfcaac5 Add splipi() to block interprocessor interrupts (which come in at IPL 5). 2001-04-20 22:28:58 +00:00
thorpej e84fefd1f1 pmap_asn_alloc(): In a multiprocessor configuration, it's possible
to arrive here referencing the kernel_lev1map without having the
RESERVED ASN -- another CPU may have caused pmap_lev1map_destroy()
to be called, and that routine only invalidates the ASN for the
CPU that called it.  So, in the MULTIPROCESSOR case, simply assign
the RESERVED ASN if we reference the kernel_lev1map rather than
asserting that we already have the RESERVED ASN.  Thanks to Bill
Sommerfeld for helping me track down the problem.

Also add a new IPI that causes a CPU to re-activate its address
space if the pmap it's using changes level 1 maps (this probably
won't happen very often, but it's correct to have it).

This makes Alpha MP kernels boot multiuser.  In fact, this commit
is being made from my dual-CPU AlphaServer 1200 running an MP kernel.
2001-04-20 16:22:33 +00:00
thorpej 1bd443444b In splx(), don't call spl0() unless the ssir != 0. 2001-04-15 23:26:05 +00:00
thorpej 00f815f803 Clean up soft interrupt related stuff a bit. 2001-04-15 23:07:34 +00:00
thorpej e964ad79cf Change the softintr implementation to be a bit more cache friendly
(though, sigh, slightly more expensive at softintr_schedule() time).
2001-04-14 00:45:13 +00:00
thorpej bf2dcec4f5 Remove the use of splimp() from the NetBSD kernel. splnet()
and only splnet() is allowed for the protection of data structures
used by network devices.
2001-04-13 23:29:55 +00:00
thorpej d74e432ed3 Make softclock a generic soft interrupt of the API is available,
adding the requisite void * argument to softclock().
2001-01-15 20:19:50 +00:00
thorpej 45de366b2e Rename __GENERIC_SOFT_INTERRUPTS to __HAVE_GENERIC_SOFT_INTERRUPTS,
and place the definition in <machine/types.h>.  This can now be used
as a flag to indicate whether or not <machine/intr.h> can be included
to get the generic soft interrupt API.
2001-01-14 23:50:28 +00:00
thorpej d85a75f583 Make sure everybody has an splvm() and equate it with splimp() (splimp()
is the historical name for this interrupt level, and the historical name
is going to go away in the near future).
2001-01-14 02:00:37 +00:00
thorpej 534e7d4454 Several changes, which get us generally further along with
multiprocessor support:
- Implement MP-safe halt.
- Make the FPU saving code more like Bill's on the i386 MP branch.
  XXX This code will no doubt be revisited again.
- Pass the cpu_info and trapframe to IPI handlers, saving some work
  in the handlers themselves, and also making it possible for the
  "pause" handler to reference register state for DDB.
- Add "machine cpu" to DDB, making it possible to reference other
  CPUs registers (and thus get e.g. a traceback) from whichever
  CPU is actually running the debugger.
- Garbage-collect "machine halt" and "machine reboot" DDB commands.
  They don't have a prayer of working properly in multiprocessor
  kernels, and didn't really work all that well in uniprocessor kernels.
2000-11-22 08:39:46 +00:00
thorpej 7f059c8e69 Move IPI processing into a separate function. 2000-11-20 19:24:36 +00:00
thorpej 137c030d5b Count individual interprocessor interrupts -- it's good to know where
they all come from.
2000-11-18 19:25:35 +00:00
thorpej 58e7a6954b Add spllock(). See spl(9) for details. 2000-08-22 19:46:26 +00:00
thorpej 2648536e0c Add experimental code for pausing other CPUs upon a CPU's
entry into the debugger.  While I'm here, add splsched()
as per spl(9).
2000-08-21 02:03:12 +00:00
thorpej 5a7793edd9 Implement MP-safe lazy FP context switching, modeled on the
way Bill Sommerfeld implemented it for x86 (and bug fixes
fed back to Bill :-)
2000-08-15 22:16:17 +00:00
thorpej 325f9ccafc Add alpha_multicast_ipi(). 2000-08-13 18:20:55 +00:00
thorpej 3eedcb3009 Whitespace police. 2000-07-13 05:47:39 +00:00
cgd c2ebb05a74 make spl0() and spllowersoftclock() return void. Also, move spl0()
prototype from param.h to intr.h.  (there were some big XXXs in param.h
that said to do that, and intr.h is included by param.h, so...)
2000-06-09 01:40:12 +00:00
thorpej 2668e3b213 Switch to the new `evcnt' mechanism for counting interrupts. Maintain
a per-CPU interrupt counter for clock, device, and interprocessor
interrupts.
2000-06-05 21:47:10 +00:00
thorpej 70dc4d8718 Un-__P'ify kernel prototypes. 2000-06-04 05:23:18 +00:00
thorpej cd423732b8 - Clean up clock interrupt code a bit, and provide a CPU_IS_PRIMARY()
macro in the MULTIPROCESSOR case (hardclock() wants it).
- Implement __GENERIC_SOFT_INTERRUPTS, and redefine the legacy
  software interrupts in terms of it.  Garbage-collect setsoftserial().
2000-06-03 20:47:36 +00:00
thorpej f6cea17c36 Rename the atomic operations to have generic machine-independent
names, and define __HAVE_ATOMIC_OPERATIONS to indicate their
existence.
2000-05-23 05:12:53 +00:00
thorpej ac93a75106 Point back to the alpha_shared_intr in the intrhand structure. This
allows platform-specific code to access the `intr_private' data via
the intrhand structure.
2000-03-19 01:46:18 +00:00
thorpej 4106b60175 Move atomic operations into <machine/atomic.h>, and make them in-line
assembly, rather than function calls.

...except alpha_atomic_testset_l(), which will go away completely once
I commit the new <machine/lock.h>.
1999-12-02 01:09:11 +00:00
thorpej df2cf70865 - Fix a botch in the IPI bitmasks (they were right-shifted by 1), and
add an IPI which causes the target CPU to perform AST processing when
  it returns to userspace.
- Add a way to get/set a private pointer in the shared interrupt header.
1999-11-29 19:58:39 +00:00
thorpej b701be7c86 Use atomic operations to manipulate the SSIR, and fix a problem introduced
with the spllowersoftclock() changes where more interrupts than necessary
were blocked while software interrupts were being processed.
1999-08-10 18:53:03 +00:00
thorpej eb20bbc780 Change the semantics of splsoftclock() to be like other spl*() functions,
that is priority is rasied.  Add a new spllowersoftclock() to provide the
atomic drop-to-softclock semantics that the old splsoftclock() provided,
and update calls accordingly.

This fixes a problem with using the "rnd" pseudo-device from within
interrupt context to extract random data (e.g. from within the softnet
interrupt) where doing so would incorrectly unblock interrupts (causing
all sorts of lossage).

XXX 4 platforms do not have priority-raising capability: newsmips, sparc,
XXX sparc64, and VAX.  This platforms still have this bug until their
XXX spl*() functions are fixed.
1999-08-05 18:08:08 +00:00
thorpej 911465b54c Restructure the IPI code a little, allowing multiple IPIs to be sent at
once.  Add a way to broadcast an IPI to all processors (except the sender,
obviously).  Add an IPI for TLB shootdown.
1999-02-24 19:17:09 +00:00
thorpej 2c50ec242f Add basic interprocessor interrupt sending and receiving code. Current
IPI functions: HALT, IMB, TBIA, TBIAP.

XXX HALT is not yet implemented, it's just a stub.
1998-09-26 00:03:51 +00:00
thorpej 01c75223d7 Minor style tweaks. 1998-09-25 22:06:33 +00:00
matt ad921921e4 Add softserial to the alpha port. This significantly improved PPP
throughput on com ports.
1998-09-21 00:33:16 +00:00
thorpej 528dab6808 Implement alpha_shared_intr_disestablish(). Simply removes the handler
fromthe list, allowing the caller to manipulate the sharing type,
if appropriate.
1998-08-01 18:52:36 +00:00
is 6054d626f9 Switching dev/ic/lpt.c to use spllpt() instead of spltty(). It doesn't use
tty structures, and on some machines (namely the DraCo internal lpt, and some
multi-i/o boards for Amigas and DraCos), tying spltty to the pretty high printer
interupt level would hurt serial performance.

On all affected ports but Amiga, spllpt() has been defined in machine/intr.h
to be spltty(), thus preserving old behaviour. Portmasters are encouraged to
change is, if they feel something else is better (e.g., one of its own were
possible).
1998-07-18 21:27:25 +00:00
thorpej de83dce0de On second thought, call that like the rest of the shared intr functions. 1998-07-07 22:24:38 +00:00
thorpej 443d238f70 Define a macro to test if a shared interrupt should be disabled after
a stray has occurred.
1998-07-07 21:37:11 +00:00
mjacob 479bc8877c Protect userland applications from the inline splraise function. 1997-11-10 18:23:50 +00:00
cgd fce829ca4b mark prototypes for static inline functions as possibly unused
(with __attribute__ ((unused))), to avoid generating warnings when
compiling without optimization but with the default warning flags.
1997-07-07 20:37:34 +00:00
cgd 891e8db771 two more slight bogons 1997-06-05 17:36:26 +00:00
cgd 1c33c6bff8 actually, declare _splraise() as an inline function, because:
(1) it was using 'max', and some functions use a variable
	    of that name (*sigh*), and
	(2) that makes it easier to be a bit trickier, and only call
	    swpipl if changing the IPL.
1997-06-05 17:31:16 +00:00
cgd 100dbb8a3c parens around macro arg (this is an old one) 1997-06-05 17:20:17 +00:00
cgd 57c012e265 make sure that splnet(), splbio(), splimp(), spltty(), splclock(),
splstatclock(), and splhigh() all _raise_ the IPL.  (splhigh() is _not_
the highest possible IPL; mcheck is...)
1997-06-05 17:08:06 +00:00
cgd 562fa9b97d clean up NetBSD RCS ID strings 1997-04-06 08:39:37 +00:00
cgd 156fe546d2 kill siroff() and resturcture do_sir() to be cleaner and more correct. 1996-12-03 17:34:47 +00:00
cgd 91c6442ca0 implement a (hack-ish) set of routines to do common chained-interrupt
handler management.  It's nasty, but three slightly different copies of
the code is worse.
1996-11-17 02:03:08 +00:00
cgd 04294813bd various cleanup, move setsoft* and spl* into intr.h. 1996-07-09 00:33:20 +00:00
cgd a37e40ef1b the Alpha implementation of <machine/intr.h> 1996-04-12 01:42:17 +00:00