Aren/NetBSD
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
278,702 Commits 606 Branches 0 Tags
Commit Graph

278702 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
jdolecek
ea48e981b3 need to clear IFF_OACTIVE after allocating more pkts in order to actually 
start processing the queue in bnx_start()
 2020-07-16 14:57:59 +00:00
jdolecek
2949b63cdc disable MSI/MSI-X for time being, it causes interrupt timeouts and needs 
to be investigated before enabling this again
 2020-07-16 14:44:43 +00:00
jdolecek
d35b28b2fa make sure the alignment of ciss_cmd matches KASSERT() in ciss_cmd() 2020-07-16 14:41:04 +00:00
jdolecek
76611ae630 revert the conversion to STAILQ, it broke execution of commands 2020-07-16 14:39:33 +00:00
simonb
ff6bcc47ef Fix variable name for BUS_DMA_DEBUG. 2020-07-16 13:32:05 +00:00
jmcneill
84507484ec FDT support for Cavium OCTEON MIPS SoCs. WIP. 2020-07-16 11:49:37 +00:00
jmcneill
c1100f3cbb Add glue for 8250 compatible UARTs. 2020-07-16 11:42:53 +00:00
jmcneill
9e222b02d1 Allow kernels to link with no console drivers 2020-07-16 11:42:17 +00:00
skrll
ce95ee174e pmapboot_enter simplication 
- bootpage_alloc in asm becomes pmapboot_pagealloc in C
- PMAPBOOT_ENTER_NOBLOCK is removed as it's not used
- PMAPBOOT_ENTER_NOOVERWRITE is removed as it's now always on
- physpage_allocator argument is removed as it's always
  pmapboot_pagealloc
- Support for EARLYCONS without CONSADDR is removed so that the identity
  map for CONSADDR is always known.

For the assembly files:
 2 files changed, 40 insertions(+), 89 deletions(-)

LGTM ryo
 2020-07-16 11:36:35 +00:00
dholland
2f503947a6 +craptacular 
(originally suggested by pgoyette)
 2020-07-16 03:08:58 +00:00
yamaguchi
f2e952a7b8 Set PCI_COMMAND_MASTER_ENABLE and PCI_COMMAND_MEM_ENABLE 
to activate the pci devices

This configuration is needed when BIOS or UEFI do not make them set.
 2020-07-16 01:20:38 +00:00
uwe
7bb9dbe9f7 Try to improve markup for better PostScript output. 2020-07-15 19:23:44 +00:00
leot
562d999853 Document unbound and unbound_chrootdir. 2020-07-15 17:55:34 +00:00
leot
093639c62c MKBSDTAR is yes by default 2020-07-15 17:46:06 +00:00
uwe
7eb2a579d9 Do not use "[...]", just "..." is enough. 
Conventionally the ellipsis already expresses optional repetition,
e.g. .Ar without arguments produces "file ...".
 2020-07-15 17:36:38 +00:00
jruoho
f1c3cdfd23 's/blacklistd/blocklistd/'. Note also blocklistd_flags. 2020-07-15 16:52:48 +00:00
jruoho
e86652a33f Note modules. 2020-07-15 16:46:11 +00:00
pgoyette
0c228d5c9c Remove now-extraneous Op since we already have Oo and Oc to enclose 
the Ar port.
 2020-07-15 16:41:16 +00:00
msaitoh
585c6ef0f7 Identify SDHC 4.1 and 4.2. From {DragonFly,Free}BSD. 2020-07-15 15:57:52 +00:00
rin
979cf575ec Fix typo. Use PRIxPADDR rather than casting. 2020-07-15 15:08:26 +00:00
jdolecek
5cd050e749 g/c unused sc_channel_raw, sc_adapter_raw 2020-07-15 14:33:58 +00:00
kim
7392fbb224 Document optional speed argument to consdev 2020-07-15 12:38:30 +00:00
kim
0224cafa34 Let consdev command also set speed 
Adapted from PR install/55490 by Sunil Nimmagadda
 2020-07-15 12:36:30 +00:00
simonb
bc6a081a98 Rename the evbmips ERLITE kernel to OCTEON now that it supports more 
than just the EdgeRouter Lite.
 2020-07-15 12:15:30 +00:00
rin
544c59d00e Add NetBSD RCSID. No functional changes. 2020-07-15 09:58:34 +00:00
rin
c09f8da7b5 Now, FPU emulation for booke and ibm4xx works fine at a level where 
all the related ATF tests pass correctly. However, there still remain
problems:

- FEX and VX bits for FPSCR cannot be modified by mcrfs, mtfsf{,i},
  and mtfsb[01].
- Invalid operations should be treated differently depending on
  FPSCR[VE].

Therefore, comment them in order not to be forgotten.

No binary changes.
 2020-07-15 09:42:43 +00:00
rin
f86c9cf0a7 Try to fix FPSCR bits in the end of emulation: 
- FPSCR[FEX] is not a sticky bit.
- Turn on FPSCR[FEX] if the emulated instruction causes invalid operation,
  and invalid operation exception is not masked out.
- FPSCR[VX] is not a sticky bit, however it should be set when at least
  one of FPSCR[VXfoo] bits (they are sticky!) is set.
- FPSCR[FX] is a sticky bit, and it should be set if FPSCR is modified by
  instructions other than mtfsf{,i}.
 2020-07-15 09:36:35 +00:00
rin
d51192cae6 Set ksi_code correctly via fpu_get_fault_code() for SIGFPE. 2020-07-15 09:22:26 +00:00
rin
1ded17e453 Expose fpu_get_fault_code() even if !PPC_HAVE_FPU, and 
adjust it to systems without FPU.
 2020-07-15 09:19:49 +00:00
rin
afdc9a380a Do not raise SIGFPE unless MSR[FE0] or MSR[FE1] is set via fenv(3). 2020-07-15 09:16:35 +00:00
rin
85c82c3d2b For booke and ibm4xx, emulate m[ft]msr in user mode, in the same 
manner as oea.

Now, user process can decide by itself whether floating-point
exception triggers SIGFPE or not via fenv(3).
 2020-07-15 09:10:14 +00:00
rin
1cac429c0f Factor out emulation code for m[ft]msr in user mode from oea, and 
adjust it for systems without FPU.

Now, it can be used from booke and ibm4xx in order to support fenv(3).
 2020-07-15 08:58:51 +00:00
lukem
960cec782f ftp.1: don't wrap "[[user@]host [port]]" 2020-07-15 08:56:05 +00:00
rin
4df424377a Treat trap instruction from userland correctly in EXC_PGM handler; 
raise SIGTRAP with TRAP_BRKPT instead of SIGILL.
 2020-07-15 08:48:40 +00:00
rin
013e0f2a9f FPSCR[FEX] is not a sticky bit; it is always cleared when read from 
userland via mffs on real hardware.
 2020-07-15 08:29:07 +00:00
rin
be3287e65b PR port-powerpc/55425 
Update comment; FPU emulation seems to work just fine now. However,
FPU-optimized code should still be avoided for better performance,
if FPU is not present.
 2020-07-15 08:14:41 +00:00
rin
c7cd6dc4df PR port-powerpc/55425 
Fix emulation for mtfsf; source register is frB here.

Now, userland processes successfully change rounding mode, by which
FPU-optimized code in OpenSSL works just fine as far as I can see.
 2020-07-15 08:10:41 +00:00
rin
e95f82412d Rename emulated_opcode() to emulate_privileged() for clarity. 
No functional changes.
 2020-07-15 07:58:26 +00:00
rin
e8cd8b2cae For trap instruction, ksi_code should be TRAP_BRKPT not TRAP_TRACE. 2020-07-15 07:54:25 +00:00
rin
877c502a15 Do not set ksi->ksi_addr twice. No functional changes. 2020-07-15 07:52:58 +00:00
rin
7a490e3644 Do not raise divide-by-zero exception when dividend is zero. 2020-07-15 07:47:27 +00:00
rin
9d4c00ef38 Do not use curlwp twice. No functional changes. 2020-07-15 07:44:34 +00:00
rin
a6140b3789 Remove old workaround foe cache problem on ibm4xx. 
The problem seems gone already.
 2020-07-15 07:37:25 +00:00
msaitoh
ec8a901c58 Add missing note about Intel I219 LM10-LM15 and V10-V14. 2020-07-15 02:26:07 +00:00
msaitoh
e8c2c44713 G.C. comment. 2020-07-15 01:42:27 +00:00
jmcneill
3fc11eecb7 Fixup OpenSimpleReadFile usage: 
- The "EFI_DEVICE_PATH **FilePath" parameter can change, so do not free
   the output. This was causing crashes on U-Boot when attempting to load
   boot.cfg, even if it didn't exist.
 - Allocate the SIMPLE_READ_FILE in advance and store a pointer to it in
   struct open_file.
 2020-07-15 00:51:40 +00:00
jdolecek
67160b8692 note ciss(4) adapter match update 2020-07-14 17:40:10 +00:00
jdolecek
5b894df5c4 update list of matched adapters 2020-07-14 17:39:19 +00:00
jdolecek
07e9b09b06 match newer HP Smart Array controllers, list from FreeBSD 2020-07-14 17:23:58 +00:00
jdolecek
b45e8e8136 fix __arraycount() parameter 2020-07-14 17:23:27 +00:00