Commit Graph

346 Commits

Author SHA1 Message Date
rjs ce385ae9b3 Add CPU IDs for PXA B2 and C0 steppings. 2003-02-14 16:00:33 +00:00
chris 3e2914e858 bus dma memory is allocated as M_DMAMAP so free it as M_DMAMAP, not DEVBUF. 2003-02-03 23:34:50 +00:00
wiz cd68fb44fb guarantee, not guarentee. Idea from miod@openbsd. 2003-02-02 10:24:38 +00:00
thorpej 23bc250391 Merge the nathanw_sa branch. 2003-01-17 21:55:23 +00:00
wiz 7e681f7063 interrupt with two rs. 2003-01-06 13:04:54 +00:00
wiz 5e442fbbdd specified, not specifed. 2003-01-06 12:38:47 +00:00
thorpej 074858daeb Fiddle with current_intr_depth in assembly code again. Because we
have just pushed a frame, we can make some assumptions that the
compiler cannot as easily make, and can thus do it slightly more
efficiently.
2003-01-03 00:38:16 +00:00
thorpej b33e60be39 Clean up evbarm interrupt support a little:
* Define an ARM_INTR_IMPL option, which specifies a header file
  describing the interrupt implementation for the platform.  Use
  this instead of the list of EVBARM_BOARDTYPE checks.
* Make the s3c2xx0 interrupt dispatch code a bit more generic, and move
  it to a generic location so that other platforms can use it.

This eliminates all uses of the EVBARM_BOARDTYPE stuff, so delete it.
2003-01-02 23:37:53 +00:00
reinoud 779842e0f8 Remove spurious declaration of bootconfig structure since that is already
done in bootconfig.h
2002-12-28 20:40:21 +00:00
chris 01bbc5d994 Add a debug assert that wired pages provide protection flags in the flags
argument as well.

Also update a couple of debug messages to NPDEBUG.
2002-11-24 01:09:09 +00:00
chris 3dd552c1b2 Fix's DEBUG kernel's not making it into multiuser on cats. (as spotted by
nick)
When wiring a page with pmap_enter you must supply the protection in the
flags as well as in the prot.
2002-11-24 01:07:47 +00:00
chs 4b2625143d change uvm_uarea_alloc() to indicate whether the returned uarea is already
backed by physical pages (ie. because it reused a previously-freed one),
so that we can skip a bunch of useless work in that case.
this fixes the underlying problem behind PR 18543, and also speeds up fork()
quite a bit (eg. 7% on my pc, 1% on my ultra2) when we get a cache hit.
2002-11-17 08:32:43 +00:00
chris 164b37a80c Tweak a few minor things:
when looking to reenable caching, only do so if all the pages aren't already
cached.
Convert some ints to unsigned int.  (scarily this actually shows the biggest
decrease in timing for my benchmark, I guess the compiler can optimise better)
2002-11-12 22:14:21 +00:00
chris e8cceb3e82 gratuitous whitespace and de-__P'ing. No functional change. 2002-11-11 20:34:03 +00:00
chris 2fc7aadded A few minor tweaks.
Use pmap_free_pvs in pmap_remove, should save on the overhead of freeing
each pv on it's own.

Correctly set ptp when calling pmap_enter_pv, this adds more overhead, but
the effect is minimal.  Timings show that it increases gmake's make configure
step from 2:07.90 to 2:08.90.  I've more optimisations planned that should
negate this increase.
2002-11-11 09:34:44 +00:00
chris cf54ec0397 Remove unused pa variable (it's assigned but not used any more) 2002-11-11 08:58:05 +00:00
jdolecek c82ab2eb79 now that mem_no is emitted by config(8), there is no reason to keep
copy of more or less identical iskmemdev() for every arch; move the function
to spec_vnop.c, and g/c machine-dependant copies
2002-10-26 13:50:17 +00:00
jdolecek e0cc03a09b merge kqueue branch into -current
kqueue provides a stateful and efficient event notification framework
currently supported events include socket, file, directory, fifo,
pipe, tty and device changes, and monitoring of processes and signals

kqueue is supported by all writable filesystems in NetBSD tree
(with exception of Coda) and all device drivers supporting poll(2)

based on work done by Jonathan Lemon for FreeBSD
initial NetBSD port done by Luke Mewburn and Jason Thorpe
2002-10-23 09:10:23 +00:00
bsh d5fb42a86c non-inline version of atomic_{set,clear}_bit(), defined when
ATOMIC_SET_BIT_NONINLINE_REQUIRED is defined.
(extracted from arm/arm32/locore.S)
2002-10-19 12:46:57 +00:00
bsh 7b6639153c make atomic_{set,clear}_bit() inline for arm32 ports, and
add <machine/atomic.h> for them.
2002-10-19 12:22:33 +00:00
bjh21 a531a4ae8e Undo recent cpu_switch register usage changes in order to decrease nathanw_sa
merge pain.
2002-10-19 00:10:53 +00:00
bjh21 7dd8880e90 The grand cpu_switch register reshuffle!
In particular, use r8 to hold the old process, and r7 for medium-term
scratch, saving r0-r3 for things we don't need saved over function
calls.  This gets rid of five register-to-register MOVs.
2002-10-18 23:06:33 +00:00
bjh21 3d1b6867f0 In cpu_switch(), stack more registers at the start of the function,
and hence save fewer into the PCB.  This should give me enough free
registers in cpu_switch to tidy things up and support MULTIPROCESSOR
properly.  While we're here, make the stacked registers into an
APCS stack frame, so that DDB backtraces through cpu_switch() will
work.

This also affects cpu_fork(), which has to fabricate a switchframe and
PCB for the new process.
2002-10-18 21:32:57 +00:00
bsh 475d72b0be fix a bug sneaked into cpu_reset() in "- . - 8 purge"
(s/mov pc,lr/mov lr,pc/)
2002-10-15 23:10:32 +00:00
bjh21 441e8907fe Switch to using the MI C versions of setrunqueue() and remrunqueue().
GCC produces almost exactly the same instructions as the hand-assembled
versions, albeit in a different order.  It even found one place where it
could shave one off.  Its insistence on creating a stack frame might slow
things down marginally, but not, I think, enough to matter.
2002-10-15 20:53:38 +00:00
bjh21 d599df9587 Continue the " - . - 8" purge. Specifically:
add	rd, pc, #foo - . - 8		->	adr	rd, foo
ldr	rd, [pc, #foo - . - 8]		->	ldr	rd, foo

Also, when saving the return address for a function pointer call, use
"mov lr, pc" just before the call unless the return address is somewhere
other than just after the call site.

Finally, a few obvious little micro-optimisations like using LDR directly
rather than ADR followed by LDR, and loading directly into PC rather than
bouncing via R0.
2002-10-14 22:32:50 +00:00
chris a28f4c93a2 Fix arm kernel build breaks for non multiprocessor systems. 2002-10-13 21:14:28 +00:00
bjh21 3d91ec9fdd Instead of "add rd, pc, #foo - . - 8", use either "adr rd, foo" or (where
appropriate) "mov lr, pc".  This makes things slightly less confusing and
ugly.
2002-10-13 14:54:47 +00:00
bjh21 85386dce51 Use cpu_number() to find curpcb rather than assuming we're on CPU 0. 2002-10-13 14:24:09 +00:00
bjh21 75248cc7a1 It appears that MI code requires ci_cpuid to be the CPU number of the CPU
in question, whereas the ARM code was using it to hold the model
identification.  To fix this, rename:

ci_cpuid -> ci_arm_cpuid
ci_cputype -> ci_arm_cputype (for consistency)
ci_cpurev -> ci_arm_cpurev (ditto)
ci_cpunum -> ci_cpuid

This makes top(1) give correct CPU numbers in its "STATE" column (all 0 for
now).
2002-10-13 12:24:57 +00:00
bjh21 d8fd346734 Remember the location of each CPU's idle PCB in struct cpu_info.
Move allocation of the idle PCB from hydra.c to cpu.c and add some
extra initialisation from cpu_fork().
2002-10-12 21:06:46 +00:00
bjh21 a7385c575f Move curpcb into struct cpu_info in MULTIPROCESSOR kernels. 2002-10-12 12:20:08 +00:00
bjh21 6ae19cc8cd Use ADR rather than an explicit ADD from PC. 2002-10-09 22:28:03 +00:00
bjh21 67ba9f99bf Remove an outdated register assignment comment. 2002-10-08 23:48:24 +00:00
bjh21 3832819227 Minimal changes to allow a kernel with "options MULTIPROCESSOR" to compile
and boot multi-user on a single-processor machine.  Many of these changes
are wildly inappropriate for actual multi-processor operation, and correcting
this will be my next task.
2002-10-05 13:46:57 +00:00
bjh21 b828507087 constify various string tables. 2002-10-01 22:33:10 +00:00
provos 0f09ed48a5 remove trailing \n in panic(). approved perry. 2002-09-27 15:35:29 +00:00
thorpej 71404bb533 Don't include <sys/map.h>. 2002-09-25 22:21:01 +00:00
chs f01058c887 rename the existing pmap_remove_all() here to pmap_page_remove()
(ala the x86 pmap) to avoid conflicting with the new pmap interface
function of the same name.
2002-09-22 07:56:57 +00:00
nathanw 2cab03d64a In the fault handler, record growth of the stack, so that core dumps
actually contain the entire stack.
2002-09-21 00:29:04 +00:00
gehenna 77a6b82b27 Merge the gehenna-devsw branch into the trunk.
This merge changes the device switch tables from static array to
dynamically generated by config(8).

- All device switches is defined as a constant structure in device drivers.

- The new grammer ``device-major'' is introduced to ``files''.

	device-major <prefix> char <num> [block <num>] [<rules>]

- All device major numbers must be listed up in port dependent majors.<arch>
  by using this grammer.

- Added the new naming convention.
  The name of the device switch must be <prefix>_[bc]devsw for auto-generation
  of device switch tables.

- The backward compatibility of loading block/character device
  switch by LKM framework is broken. This is necessary to convert
  from block/character device major to device name in runtime and vice versa.

- The restriction to assign device major by LKM is completely removed.
  We don't need to reserve LKM entries for dynamic loading of device switch.

- In compile time, device major numbers list is packed into the kernel and
  the LKM framework will refer it to assign device major number dynamically.
2002-09-06 13:18:43 +00:00
jdolecek 8839507f5b whitespace fix past __KERNEL_RCSID() 2002-09-05 18:34:00 +00:00
thorpej 212cb9f78d Add machine-dependent bits of RAS for arm32. 2002-08-31 03:07:32 +00:00
thorpej 139cdc3125 Make nbuf, nswbuf, and bufpages unsigned. Make all operations on these
variables unsigned, and update places where their values are printed.
2002-08-25 20:21:33 +00:00
thorpej ffdedb6d80 In pmap_map_in_l1() and pmap_unmap_in_l1(), make sure that the VA
that is passed in is already aligned to a 4M super-section.
2002-08-24 03:10:40 +00:00
thorpej d158b3a37a When we allocate a PTP, make sure the offset we specify is for
the 4M super-section that the PTP will map, not some random 1M
chunk of it.  This gives the PTP hint code a much better chance
to working properly, and allows us to tidy up the code that
flushes a PTP from the cache in pmap_destroy().
2002-08-24 02:50:53 +00:00
thorpej 77a6866508 Enable caching on kernel and user page tables. This saves having
to do uncached memory access during VM operations (which can be
quite expensive on some CPUs).

We currently write-back PTEs as soon as they're modified; there is
some room for optimization (to write them back in larger chunks).
For PTEs in the APTE space (i.e. PTEs for pmaps that describe another
process's address space), PTEs must also be evicted from the cache
complete (PTEs in PTE space will be evicted durint a context switch).
2002-08-24 02:16:30 +00:00
thorpej 6cc7c1c1ff * Add PTE_SYNC() and PTE_SYNC_RANGE() macros. These don't actually do
anything yet.
* Use PTE_SYNC() and PTE_SYNC_RANGE() in some obvious places, i.e.
  where vtopte() is used.
2002-08-22 01:13:53 +00:00
thorpej 574a9cc019 Use a pool cache for PT-PTs. 2002-08-21 21:22:52 +00:00
thorpej 5fddbbe3d5 Do cached memory access to L1 tables, making sure to write-back the
cache after any L1 table modifications.
2002-08-21 18:34:31 +00:00