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3400 Commits

Author SHA1 Message Date
fvdl
a3ff3a3038 Bump daddr_t to 64 bits. Replace it with int32_t in all places where 
it was used on-disk, so that on-disk formats remain the same.
Remove ufs_daddr_t and ufs_lbn_t for the time being.
 2003-01-24 21:55:02 +00:00
pk
f65446d08d When stopping a CPU, clear its bit from cpu_ready_mask. 2003-01-23 22:33:41 +00:00
pk
a6a16741fe Optimize xcall() et.al. further by maintaining a cpuset mask of all CPUs 
marked ready. This saves repeated testing for NULL pointers and the
CPUFLG_READY flag.
Also use a separate flag variable to signal xcall completion. This saves a
load and a pipeline stall.
 2003-01-23 19:54:35 +00:00
pk
a799bdd88d GC the per-CPU message lock. 
Move the level 15 msg area further down the cpuinfo structure, as it's
used infrequently.
 2003-01-23 18:49:08 +00:00
pk
39ce68a44b bogusintr: print cpu number. 2003-01-23 14:56:06 +00:00
pk
22acc2a827 Shave some code off xcall(). 2003-01-23 14:54:33 +00:00
pk
40a1653fc2 pmap_kenter_pa4m: like pmap_enk4m(), we can use setpte4m(). 
ctx_free: fix cache flush context for sun4/sun4c.
 2003-01-23 12:48:53 +00:00
pk
698ca6fb6f LWPify cpu_debug_dump(). 2003-01-23 11:50:50 +00:00
pk
9d33cc7115 Set the interrupt target to the current CPU when directly accessing 
the chip for console I/O.
 2003-01-22 22:00:39 +00:00
pk
53c776f062 Add functions to set & get the interrupt target CPU. 2003-01-22 21:58:28 +00:00
sjg
b3d7df8002 Don't hide bootmid behind MULTIPROCESSOR. 2003-01-21 06:18:41 +00:00
pk
26eedde15b srmmu_cache_flush: when flushing per-page and doing more than one page, 
we might be crossing a segment boundary.
 2003-01-20 22:15:54 +00:00
pk
d823499ff4 pmap_enter4m: when installing a new PTE we don't need to invoke the elaborate 
TLB de-map protocol.  In the relatively infrequent case where this function
must update an existing mapping, do the de-map explicitly before installing
the new PTE value.
 2003-01-20 22:03:54 +00:00
pk
ab9a8ae184 Set the system-wide cache aliasing distance according to the largest cache 
found on the CPU modules (hypersparc & cypress).

Vikings have a physically indexed cache, so don't bother with computing an
aliasing distance (leaving cache_alias_dist zero disables the BAD_ALIAS macro).
 2003-01-20 21:56:34 +00:00
pk
b4a0aebea2 Add SUN4D case for cache alias macros. 2003-01-20 21:43:38 +00:00
pk
353e527861 Remove the restriction that the boot CPU must be the first CPU in the order 
as it is presented by the PROM. This is actually amazingly less trivial
than it looks at first, since the finding the Module ID that's currently
executing your code is specific for each module type and/or manufacture.
 2003-01-20 20:51:33 +00:00
pk
18f455c44f Replace some more VA2PA(<static_addr>) calls with PMAP_BOOTSTRAP_VA2PA() 2003-01-20 15:45:40 +00:00
pk
5815e88f83 De-couple some MULTIPROCESSOR and SUN4M/SUN4D dependencies. 2003-01-20 12:06:49 +00:00
pk
5be63cb4a3 xcall(): two more printf => printf_nolog 2003-01-20 00:55:52 +00:00
thorpej
c464d72f40 Merge the nathanw_sa branch. 2003-01-18 06:44:56 +00:00
pk
4d7731a177 cpu_switch: 
* return `switched to same process' only if that process was actually
  already on a run queue when we entered.
* skip the switch to the idle stack if we can switch immediately
* .. and because of this, don't release the scheduler lock until after
  we've fully switched to the new process's stack.
 2003-01-17 14:49:45 +00:00
pk
d352e8ce9c pmap_deactivate(): only update the pmap's cpuset if need to. 2003-01-17 14:15:17 +00:00
pk
1d67b9c75a Don't grab the kernel lock for system timer interrupts; this mostly prevents 
stalls in system time processing.

XXX - deal with non-atomic global time variables updates later.
 2003-01-17 10:36:19 +00:00
pk
2252ed574d mp_{pause,resume,halt}_cpus(): check for cpus==NULL. 2003-01-16 17:21:43 +00:00
pk
c454f450b1 Define a MP version of callrom(). 2003-01-16 16:58:52 +00:00
pk
7d4c3f7430 Remove some accidental garbage. 2003-01-16 16:58:23 +00:00
pk
72c28f7bb7 Rename the current mp_{pause,resume}_cpus() => mp_{pause,resume}_cpus_ddb(). 
Implement mp_pause_cpus/mp_resume_cpus on top of the PROM services.
 2003-01-16 16:57:43 +00:00
pk
58b50d0643 Read the CPU mailbox in the level 15 soft interrupt handler and respond 
to idle and stop requests.
 2003-01-16 16:27:48 +00:00
pk
b418a6a59d Some PROMs get really uneasy if the prom_reboot() function is called 
after the other CPUs have already return into the PROM through prom_cpustop().
So don't do it; try to halt the other CPUs only when an actual `halt'
is requested.

My guess in this case is that the PROM does not expect its original boot
CPU to call prom_cpustop(0), or possibly treats it as the equivalent of
a prom_halt() which is then called again by some other CPU. In any case,
the result is garbage.
 2003-01-16 16:20:20 +00:00
pk
f312ee5f9a What do you know.. the prom_cpu{stop,idle,resume} function appear to be 
returning a success/fail flag. For now, use it to be informative.
 2003-01-16 16:10:44 +00:00
pk
5e231ddd1c * Implement mp_halt_cpus() 
* xcall: use printf_nolog()
 2003-01-16 14:49:08 +00:00
pk
72286d4202 Definitions of some OBP generated CPU mailbox messages. 2003-01-16 14:43:07 +00:00
pk
26fa27a910 Fix reboot options handling; now one-letter kernel names can also be booted. 2003-01-16 11:33:21 +00:00
pk
a5cea9e740 On Hypersparc MP machines, we need to flush the TLB after a page cache flush. 
While the pmap functions take care of properly ordering cache and TLB flushes,
not all TLB flush requests are sent to all CPUs (due to per CPU pmap tracking)
while cache flushes are always broadcast.

XXX: need to investigate pmap tracking for cache flush operation as well.
 2003-01-15 22:56:32 +00:00
pk
5bb3d93538 srmmu_cache_flush: switch MMU contexts in all places where it matters. 
(incidentally, this also makes Hypersparc MP machines mostly go).
 2003-01-15 16:42:27 +00:00
pk
a458d9f040 Fix compiler warning induced by last change. 2003-01-15 06:57:12 +00:00
pk
9eb63b3b94 statintr: if interrupting code running below IPL_SCHED, call schedintr() 
directly, saving the overhead of an extra soft interrupt.
 2003-01-14 23:00:59 +00:00
pk
c8226e1ce0 Define spllowerschedclock(). 
To be used in the same spirit as spllowersoftclock().
 2003-01-14 22:58:00 +00:00
pk
d45f77c6c8 Add CLKF_LOPRI() macro that allows a (timer) interrupt handler to determine 
whether it is interrupting code running at a given IPL level.
 2003-01-14 22:54:53 +00:00
pk
ee7e8274a6 xcall: raise IPL to splsched() to prevent interrupts that take schedlock. 
Otherwise we have a locking order problem with schedlock and xmsglock.
 2003-01-14 17:30:55 +00:00
pk
18cd92ffe3 (Re)initialise the pmap structure fields that are not preserved on the 
pmap pool cache all in one place.
 2003-01-14 13:56:07 +00:00
pk
b50058b483 Broadcast I-cache flush in the `Unimplemented Flush' trap handler. 2003-01-13 20:00:34 +00:00
pk
b4a1c0f6a0 Reset ddb_cpuinfo when leaving DDB. 2003-01-13 19:44:53 +00:00
pk
167ce8e6d3 Fix stack tracing once again. 
Also check for trap frame boundaries when fetching the return address.
 2003-01-13 19:44:06 +00:00
pk
df4b5f766b Remove UNLOCK_XPMSG() before cpu_halt(); it's not compatible with LOCKDEBUG 
and it wan't chique in any case.
 2003-01-13 16:59:17 +00:00
mrg
8d9571d120 remove cpu_hatched, cpu_hatch_sc and cpu_hatchstack. the first can use 
the cpi->flags, the second is unused and the third is also cpi-idle_u.
 2003-01-13 15:50:50 +00:00
pk
5642428f4e Use print_nolog() from xcall(), to avoid confounding things even further 
by re-entering the scheduling code to wakeup syslog waiters.
 2003-01-13 15:01:16 +00:00
pk
4641d55697 Halt any other CPUs in cpu_reboot(). 2003-01-13 01:35:45 +00:00
pk
2684c88122 fpulock: encapsulate required IPL raise in the FPU LOCK/UNLOCK macros. 2003-01-12 16:29:00 +00:00
uwe
24780840a1 Account softintr_common as uvmexp.softs, not uvmexp.intrs. 2003-01-12 06:11:01 +00:00