thorpej
|
f0d792297e
|
Define the AMD K6 cache/write-combinding control register MSR.
|
2001-09-19 00:30:11 +00:00 |
|
thorpej
|
ebbd9cd428
|
Add some more CPUID feature bits.
|
2001-08-01 18:47:38 +00:00 |
|
wiz
|
a9356936b4
|
seperate -> separate
|
2001-07-22 13:33:58 +00:00 |
|
wiz
|
f3f6c5b675
|
accessible' only has one a'.
|
2001-06-19 12:52:20 +00:00 |
|
fvdl
|
b4b5dc533d
|
Add fxsr CR4 bits.
|
2001-06-19 09:12:49 +00:00 |
|
enami
|
5575e1f704
|
Print cpu features line only when corresponding part of bits are set.
|
2000-12-21 05:11:00 +00:00 |
|
fvdl
|
76e330bdb3
|
Fix typo.
|
2000-09-20 22:59:44 +00:00 |
|
thorpej
|
b9b07590ec
|
Define some 586-class CESR MSR bits.
|
2000-09-13 04:44:27 +00:00 |
|
thorpej
|
e2cc69026a
|
Add 686-class performance counter events.
|
2000-09-13 03:37:04 +00:00 |
|
thorpej
|
f4f96605b9
|
Add/correct some MSRs, from Intel Architecture Software Developer's Manual,
Volume 3 (System Programming).
|
2000-03-27 23:15:57 +00:00 |
|
thorpej
|
b05796c812
|
Add some Model Specific Register definitions. From FreeBSD.
|
2000-03-24 19:06:07 +00:00 |
|
sommerfeld
|
c86b5b3d08
|
Add new CPU feature flags (up through recent Pentium III and Celerons)
|
1999-12-13 01:31:30 +00:00 |
|
chuck
|
0b471e545e
|
add bits for %cr4 and cpu_feature [from freebsd and www.sandpile.org]
|
1997-09-05 22:28:12 +00:00 |
|
cgd
|
022ee8f7fe
|
new RCS ID format.
|
1994-10-27 04:14:23 +00:00 |
|
deraadt
|
ffb9d6e173
|
document cyrix configuration registers
|
1994-08-03 21:39:16 +00:00 |
|
mycroft
|
736870802e
|
Add some more constants.
|
1994-05-24 11:54:24 +00:00 |
|
mycroft
|
2250fff236
|
Cleanup and garbage collection; nothing significant. From magnum branch.
|
1993-12-20 05:25:02 +00:00 |
|
cgd
|
30177b538f
|
add rcsids to everything and clean up headers
|
1993-05-22 07:56:12 +00:00 |
|
deraadt
|
9948c39839
|
npx patches from Bruce Evans. patchkit 10002
|
1993-05-09 23:02:34 +00:00 |
|
cgd
|
61f282557f
|
initial import of 386bsd-0.1 sources
|
1993-03-21 09:45:37 +00:00 |
|