Commit Graph

5 Commits

Author SHA1 Message Date
thorpej cc2c493bc4 Use PAGE_SIZE rather than NBPG. 2003-04-02 07:35:54 +00:00
scw 87897c05fe Qualify ptel and tlbcookie fields with volatile since they are
modified by the TLB miss handler.
2002-12-06 10:10:48 +00:00
scw a3885e9bdd - Change VM_MIN_KERNEL_ADDRESS to start at KSEG1 instead of KSEG0.
- Overhaul the TLB management code such that we now keep track of
   the exact TLB slot at which a mapping was inserted, both for user-
   space and kernel mappings. This addresses #2 on the TODO list.
2002-11-23 09:25:54 +00:00
scw 9bbc15e3a1 Add a SH5_PTEL_CACHEABLE() macro which evaulates TRUE if the specified
PTEL describes a cacheable mapping.
2002-10-07 14:42:31 +00:00
scw 59474a8c82 NetBSD, meet the SH-5 cpu.
SH-5, meet NetBSD.

Let's hope this is the start of a long and fruitful relationship. :-)

This code, funded by Wasabi Systems, adds initial support for the
Hitachi SuperH(tm) SH-5 cpu architecture to NetBSD.

At the present time, NetBSD/evbsh5 only runs on a SH-5 core simulator
which has no simulated devices other than a simple console. However, it
is good enough to get to the "root device: " prompt.

Device driver support for Real SH-5 Hardware is in place, particularly for
supporting the up-coming Cayman evaluation board, and should be quite
easy to get running when the hardware is available.

There is no in-tree toolchain for this port at this time. Gcc-current has
rudimentary SH-5 support but it is known to be buggy. A working toolchain
was obtained from SuperH to facilitate this port. Gcc-current will be
fixed in due course.

The SH-5 architecture is fully 64-bit capable, although NetBSD/evbsh5 has
currently only been tested in 32-bit mode. It is bi-endian, via a boot-
time option and it also has an "SHcompact" mode in which it will execute
SH-[34] user-land instructions.

For more information on the SH-5, see www.superh.com. Suffice to say it
is *not* just another respin of the SH-[34].
2002-07-05 13:31:28 +00:00