4a126d9937
finish moving common arm32 bits out into arm/arm32.
2001-07-28 15:08:10 +00:00
0847de74d2
Add copyright notices. Use MEMC_PHYS_BASE rather than 0x02000000.
2001-07-28 13:49:25 +00:00
ddf906b00d
Use ld -N (OMAGIC), since this saves the 32k of RAM (by not putting a gap
...
between text and data) and means that loadfile only needs one backward seek
to load the file rather than two (which is important for gzipped kernels).
2001-07-28 13:48:32 +00:00
27f96e8440
Move the generic arm32 files into arm/arm32 from arm32/arm32, tested kernel builds on cats and riscpc.
2001-07-28 13:28:03 +00:00
9c823196e0
Change -x into -X for linking, it makes traces more meaningful.
2001-07-28 13:24:24 +00:00
6be7c15373
bcopy -> memcpy
2001-07-28 13:21:26 +00:00
88fbdda31f
bcopy -> memcpy
2001-07-28 13:08:34 +00:00
f3b9fa04ed
Only declare kernel objects ifdef _KERNEL.
2001-07-28 12:53:06 +00:00
ec79dd3942
Add installation glue.
2001-07-28 12:44:54 +00:00
99297e58cb
We no longer have MI ncr(4) driver.
2001-07-28 12:42:34 +00:00
37dc65af43
bzero->memset
2001-07-28 12:29:58 +00:00
338f184d45
Fixup stray interrupt handler's return address.
2001-07-28 12:28:56 +00:00
690c5b1ae3
Enable the Acard UIDE controllers by default.
...
My WDC MDMA-only (non-UDMA) drives did not work on the Acard controllers,
but it turns out that the problem was not Acard specific.
These WDC drives do not work on the ESS ISAPnP wdc port nor on
macppc obio wdc port neither, and another Quantum MDMA-only drive
works fine on the Acard.
These WDC drives work fine on my i386 pciide (which is initialized
by the BIOS), so maybe we have to do something in MI wdc to initialize
such drives properly...
2001-07-28 12:07:11 +00:00
0481f078a0
bzero -> memset
2001-07-28 11:17:15 +00:00
d750508a87
Hook the error interrupt only once, otherwise we'd fail when hooking
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the interrupt for the 2nd DRAM board where two boards are present.
2001-07-28 08:30:23 +00:00
218b61dcd1
Change clock_t and time_t to more LP64 friendly types.
2001-07-28 07:43:07 +00:00
36dc943f75
Change ARM-ELF to LP64 friendly types.
2001-07-28 07:42:28 +00:00
f47c5bbd3d
Under ELF, change clock_t and time_t to int's (more LP64 friendly).
2001-07-28 05:04:45 +00:00
888b31fb38
indent fix
2001-07-28 01:13:56 +00:00
4ec277f9ee
regen
2001-07-28 00:33:43 +00:00
70cd305a5d
3c556 V.90 MiniPCI modem
2001-07-28 00:33:01 +00:00
9139a37393
New arm26 bootloader. Mostly a translation of BBBB into C, using libsa so
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we get goodies like gzipped kernels for free.
2001-07-27 23:13:49 +00:00
0ad24007df
Add assorted stuff that we need in order to shut RISC OS down cleanly.
2001-07-27 23:09:15 +00:00
fab087b3a2
Tell the MII layer to advertise PAUSE capability, and configure
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the chip's PAUSE threshold.
2001-07-27 22:46:20 +00:00
7459c35d44
Clean up 1000BASE-SX autonegotiation, and add a way to advertise
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PAUSE capability.
2001-07-27 22:44:59 +00:00
27ae3aab7c
Blah, yet another nit: s/irq/ipl/
2001-07-27 21:56:10 +00:00
ea00e7cda2
Don't bother trying to initiate a DRAM scrub on startup as it requires
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frobbing with registers which are marked as "For Test Purposes [only]".
2001-07-27 21:54:07 +00:00
9e74a14e1f
Add a sysctl to frob sb_max.
2001-07-27 21:19:09 +00:00
d8372315a2
Rudimentary OS_Byte support, and an extra VDU variable.
2001-07-27 21:10:04 +00:00
d939fd1e55
Add support for OS_ReadVduVariables, with #defines for the variables that BBBB
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uses.
2001-07-27 20:49:09 +00:00
c184f03348
Remove Mistakenly Left In comments around some `#ifdef DIAGNOSTIC' tests.
2001-07-27 20:48:58 +00:00
a24c2adedf
Limit the heap so as to allow 4 KB of stack, which should be enough for most
...
purposes.
2001-07-27 20:48:20 +00:00
8343a1492f
Forgot to shift the DRAM Bank identifiers by four.
2001-07-27 20:33:35 +00:00
59612894e1
Now that M_TRAILINGSPACE() checks buffer writeability properly,
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we can greatly simplify sbcompress(). Slightly modified from
a similar change in FreeBSD.
2001-07-27 19:27:49 +00:00
f169034d7f
Fix a braino in the check for a jumper across pins 1-2 of J1 (mvme1[67]7).
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Spotted by Chuck Silvers.
2001-07-27 18:58:23 +00:00
9ac6178585
memc attaches at mainbus now.
2001-07-27 18:40:27 +00:00
7e2f2acb8e
Flesh out the memory controller driver (at least for the MCECC chip)
...
and attach it at mainbus since it depends both PCCChip2 and VMEChip2
(or the VMEChip2 interrupter) starting first.
We can finally enable, detect and log DRAM ECC errors.
(The PROM disabled ECC checks by default)
2001-07-27 18:38:54 +00:00
4333749c7a
Use the bit-swapped OUI for the 5221. (Have I mentioned that I really
...
don't like how the current MII_OUI() works?)
2001-07-27 17:58:20 +00:00
773c261d65
Add a 3Com 3c905B internal PHY.
2001-07-27 17:55:34 +00:00
3d3c5fa78c
Regen; added a 3Com 3c905B internal PHY made by Broadcom.
2001-07-27 17:55:07 +00:00
4063cb411b
Fixup some Broadcom entries, add an entry for Broadcom PHY that
...
is built-in to some 3Com 3c905B cards.
2001-07-27 17:54:40 +00:00
1f1c7b96d8
Fix some comments and remove an unused define. Partially from OpenBSD.
2001-07-27 16:16:34 +00:00
aa9c31f0c3
Pull up some changes from OpenBSD's iha.c rev 1.6:
...
- rename tul_* functions/variables iha_* for consistency
- disable updating EEPROM routine, which does not work anyway
- make iha_rate_tbl[] const
2001-07-27 15:51:14 +00:00
5a7161cf2a
Pull up some changes from OpenBSD's iha.c rev 1.5:
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- minor code cleanups
- rename some functions for better consistensy/clarity
- consolidate extended message generation into new function
- a couple of minor code clarifications to eliminate extra return
statements and make absolutely sure actscb is NULL during a reselect
2001-07-27 15:10:56 +00:00
f5abeb5b4b
Set MAXPHYS to 64k instead of 63k.
2001-07-27 12:58:21 +00:00
39a7595b28
Calculation of unibus map register size was wrong.
2001-07-27 12:57:20 +00:00
182b1e5191
do not #ifdef KEY_DEBUG in header. sync with kame
2001-07-27 04:48:13 +00:00
99020323e6
Nuke the 5 NULL parameters from rf_DoAccess(). Observe that 4 of
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the variables are passed directly to rf_AllocRaidAccDesc(), and the 5th
isn't even used. Hunt them down and nuke them too.
2001-07-27 03:30:07 +00:00
fe97433fcd
All CORKSCREWs have MII.
2001-07-27 02:33:34 +00:00
f532a911f0
Chipset is CORKSCREW for the 3c515.
2001-07-27 02:13:26 +00:00
chris