multi-port cards (which need the shared-rom/intr stuff) and single-port cards
(which must not have it). previously we enabled sharing for all adaptec cards,
which caused problems if you had multiple single-port cards on the same PCI bus.
pci_attach_args *" instead of from four separate parameters which in
all cases were extracted from the same "struct pci_attach_args".
This both simplifies the driver api, and allows for alternate PCI
interrupt mapping schemes, such as one using the tables described in
the Intel Multiprocessor Spec which describe interrupt wirings for
devices behind pci-pci bridges based on the device's location rather
the bridge's location.
Tested on alpha and i386; welcome to 1.5Q
98715* series.
The MX98715AEC-[C,E] use a different location in the serial eerom for
LED control, and programming it with the original location's values
caused unpredictable behavior.
Also, start integrating fixes where media changes on an adapter
under load may fail. There's more work to be done here, but I need
to sort out our internal changes a little more carefully.
epic0 at pci0 dev 11 function 0 epic0: unable to wake up from ...
... print this:
epic0 at pci0 dev 11 function 0: unable to wake up from power state D3
cardbus_get_capability() [mirror change already made to if_tlp_pci.c]
- if_tlp_cardbus.c: If we don't find an ISV SROM, try to grab the
Ethernet address from the CIS.
- if_tlp_cardbus.c: set CardBus cards to store-and-forward mode from
the get-go.
- Put the TxThresh tables in tulipvar.h, and use them in the CardBus
and PCI front-ends to go to store-and-forward mode.
- Document the Xircom X3201-3 clone a little more.
pass 4.1 21143s, they have a 128-byte SROM, and thus use a different
SROM address size than all other pass 4.1 21143s.
A plea to hardware designers -- *please* read application notes for
the components you're using before putting your hardware together. Thanks.
this consistently, and it doesn't always work even when the chip
supports it.
- Make sure things DMA'd to the chip that the chip interprets are in
little-endian mode.
- 82C115 has a 128-bit multicast hash table, not 512-bit.
- Correct the way the MAC address is read from the SROM, after re-reading
the MX98715A Application Note.
Other semi-related changes:
- Differentiate between MX98715 and MX98715A.
- Improve the Macronix link-up/link-down detection.
ISV SROM format. For these boards, we provide the GPIO pin direction
info, a separate reset hook, and hard-wire them to MII-on-SIO.
Based on a patch submitted by Luoqi Chen <luoqi@chekov.watermarkgroup.com>.
boards which use MII for media attachment.
ISV SROM format information lifted from Matt Thomas's `de' driver.
Thanks to Dave Sainty for experimenting w/ his 21140A MII boards, and
for supplying a fix to the MII bit-bang code (PR #8382).
