Commit Graph

305 Commits

Author SHA1 Message Date
ross d963824bdc #include <machine/intrcnt.h> 1998-11-19 02:35:39 +00:00
ross bc9cb58205 Fix interrupt map for baseboard bridge. 1998-11-19 02:33:37 +00:00
mjacob 82b48f66b6 If NSIO not defined, compile errors. 1998-10-31 23:51:05 +00:00
ross e43333b7e7 Move if_ade* from alpha/pci/ to alpha/a12/ 1998-09-24 05:36:05 +00:00
ross 86f044d10e Track changes elsewhere in the PCI interface. 1998-09-23 21:20:55 +00:00
ross 55714d5b34 Update for vm_offset_t, vaddr_t sweep. 1998-09-23 21:17:17 +00:00
thorpej 1df7dffd26 Nuke an unused variable. 1998-09-01 21:28:04 +00:00
cgd d58173741d kill the last remnants of __BROKEN_INDIRECT_CONFIG. (only the pica port
used it, and it's non-working and apparently slated for replacement.)
1998-08-31 22:28:04 +00:00
cgd 3110e22945 use current bus_space interface names for barrier ops 1998-08-30 23:29:10 +00:00
thorpej c529c40718 Normalize the copyright notice on this file. 1998-08-15 20:42:25 +00:00
thorpej d5df55112a vm_offset_t -> {paddr_t,vaddr_t}, vm_size_t -> vsize_t 1998-08-14 16:50:00 +00:00
thorpej 8eeb95fce4 Implement pci_intr_disestablish(). 1998-08-01 20:25:12 +00:00
thorpej 92fa3a68ad In sio_intr_disestablish, also make sure that IRQs 0, 1, 8, and 13
default to edge-triggered, just like in the setup.
1998-08-01 19:38:29 +00:00
thorpej 0b60fda7c8 Implement sio_intr_disestablish(), and ensure that an initially-enabled
interrupt is never disabled and an initially-level-triggered interrupt
never becomes untyped.
1998-08-01 18:54:21 +00:00
thorpej f948e430bb Provide a hook for bypassing space accounting, needed to support ISA PnP
for now.
1998-07-31 04:37:02 +00:00
thorpej eb32016a95 Split up using BWX for PCI config and bus access. Default to using BWX for
the former, but not the latter.  Hopefully, this will address some problems
people have been experiencing w/ some devices on Pyxis systems when BWX
is used for bus access.  (If it's not used for PCI config access, we can
get fatal machine checks while probing behind PCI-PCI bridges!!)
1998-07-29 01:28:44 +00:00
mjacob a5e7f763c2 minor tweak, and example of how to do error insertion 1998-07-08 00:58:09 +00:00
mjacob 275fb86f8d add some error handling definitions 1998-07-08 00:40:18 +00:00
thorpej de83dce0de On second thought, call that like the rest of the shared intr functions. 1998-07-07 22:24:38 +00:00
thorpej 1ddd528346 Fix typi. 1998-07-07 22:02:57 +00:00
thorpej e82fc7d3cd The Pyxis core logic in the 164SX and 164LX seems to have problems with
stray interrupts.  Do what Digital UNIX (formerly DEC OSF/1) does; just
ignore strays.
1998-07-07 21:49:47 +00:00
thorpej ca73507d0b The Pyxis core logic in the Miata seems to have problems with stray interrupts.
Do what Digital UNIX (formerly DEC OSF/1) does; just ignore strays.
1998-07-07 21:47:49 +00:00
thorpej be83de18fd Use ALPHA_SHARED_INTR_DISABLE() to test if a shared interrupt should
be disabled after a stray.
1998-07-07 21:44:57 +00:00
jonathan 011f2bda08 defopt NS, NSIP. 1998-07-05 06:49:00 +00:00
jonathan 3751946b97 defopt INET, NETATALK. 1998-07-05 00:51:04 +00:00
thorpej 02b767eee5 Take a stab at EB66 support. An EB66 is basically an EB64+ with a
21066 LCA instead of a 21064 + APECS.
1998-06-27 10:10:51 +00:00
thorpej dff0b84aba Oops, forgot option header. 1998-06-27 08:59:03 +00:00
ross 50604bf85b Kill off some EVCNT_COUNTERS calls, since [A] it has to be rewritten anyway
before it can be useful, and [B] #ifdefs do not belong at every call site,
a common API should be defined and the implementations conditionalized, not
the calls. Duhh.

Also, remove the initial XXX mystery_icu debugging code.
1998-06-26 21:59:46 +00:00
ross a0f70c580c New platforms: Mikasa and Mikasa/Pinnacle, aka Pinkasa.
Like the 1000A, the AlphaServer 1000 has a daughtercard assembly that
integrates the CPU and core logic, so these can be ev4/apecs or ev5/cia.
New systype, and, sigh, another way of doing interrupts and another
mystery icu.

Kill off some EVCNT_COUNTERS calls, since [A] it has to be rewritten anyway
before it can be useful, and [B] #ifdefs do not belong at every call site,
a common API should be defined and the implementations conditionalized, not
all the calls. Duhh.
1998-06-26 21:45:56 +00:00
thorpej 78d7f07efd Very preliminary support for the Tadpole/DEC AlphaBook. These are basically
AXPpci33 machines + power management and a Cirrus PCI-PCMCIA controller.

There is currently no support for the power management facilities, and
the PCI-PCMCIA controller driver needs some work, but this should boot
and run from disk.
1998-06-26 05:42:34 +00:00
ross 63e87b1a8e New platforms: Noritake, Pintake, and Corelle. Sometimes these are ev4/apecs,
sometimes they are ev5/cia.
1998-06-24 01:38:59 +00:00
ross 49d5ae18ba Call pci_1000a_pickintr() like on other platforms, but for 1000a expand
the iot, memt, and pc in the call so that pci_1000a_pickintr() (and the
other routines in that module) do not need to be aware of the core logic
type just to pass down memory and I/O space tags or to call the decompose
function.
1998-06-24 01:32:06 +00:00
thorpej e2ebc10c2d Duuuh! Align the SGMAP page tables to 32K, not 32M. 1998-06-23 02:31:05 +00:00
thorpej 02182100df Use config_defer(). 1998-06-09 18:49:33 +00:00
thorpej 8dedb90f13 The ISA chipset must persist; it's required after autoconfig time. 1998-06-08 23:49:05 +00:00
thorpej 14df007174 Oops, don't forget to fill in *addrp. 1998-06-07 00:29:29 +00:00
thorpej 0890af5ca8 Only disable an interrupt line after MAXSTRAYs if there is no handler
attached; we get stray interrupts on PCI devices sometimes, for some
unknown reason.  (Similar problem exists on the 164SX, which also has
a Pyxis.)
1998-06-06 23:29:23 +00:00
thorpej 331a7f56c1 Remove some debugging code no longer relevant now that we have DMA
window chaining.
1998-06-06 23:11:52 +00:00
thorpej eabad6b572 Implement bus_space_{alloc,free}() for swiz PCI I/O space. 1998-06-06 22:44:46 +00:00
thorpej 7a6d646c9b Implement bus_space_{alloc,free}() for BWX bus space. 1998-06-06 22:28:16 +00:00
thorpej 04ba8480ae Use REGVAL64() to frob the Pyxis interrupt mask register. 1998-06-06 20:42:36 +00:00
thorpej 098dd211c7 Define a REGVAL64() for some Pyxis registers. 1998-06-06 20:40:14 +00:00
thorpej 85d08836f1 - Don't call *_dma_init() twice; there's no need to. Just do it in *attach().
- Display Pyxis revision properly.
1998-06-06 01:33:44 +00:00
thorpej c0fa3c6ac4 Don't call *_dma_init() twice; there's no need to. Just do it in *attach(). 1998-06-06 01:33:23 +00:00
thorpej 9331237596 Oops, turn off some debugging printfs. 1998-06-05 21:47:14 +00:00
thorpej bf8523f4e4 - Egads! There are Pyxis "Pass 1" chips that do not have the DMA bug!
Use the check recommended by the Digital Workstation engineers; look
  for Miata 1 systems (i.e. with Intel SIO).  From Andrew Gallatin.
- Update copyright (Pyxis and BWX).
1998-06-05 19:25:19 +00:00
thorpej f251e3372d Don't attempt to map the PCI IDE interrupt at bus 0 device 11 on the
AlphaPC 164 and AlphaPC 164LX - these are wired to compatibility mode.
1998-06-05 19:15:41 +00:00
thorpej 1aa688234e Miata 1 has an Intel SIO at bus 0 device 7 and a CMD PCI IDE at bus 0
device 4.  Miata 1.5 and Miata 2 have a Cypress at device 7 and PCI IDE
at functions 1 and 2 of the Cypress (like the PC164SX).  These on-board
PCI IDE controllers are wired to compatibility mode, so don't bother
trying to map the interrupt.
1998-06-05 19:04:51 +00:00
thorpej c072110af0 Actually, I did use a few of them on this file (I wasn't clear enough
in my mail to Ross, I guess...)
1998-06-05 17:42:53 +00:00
thorpej bb362059ac On Pass 1 Pyxis, disable PCI Read Prefetching, and warn the user about
the DMA bug that exists on this Pyxis revision.
1998-06-05 17:24:11 +00:00