- In the console getc routine, block until a character becomes ready
(no, really, we mean it). This routine should _never_ time out.
- In the console putc routine, if the UART has trouble, do NOT proceed
to print a diagnostic message, which would recursively invoke the
console putc routine ad nauseum.
UVM was written by chuck cranor <chuck@maria.wustl.edu>, with some
minor portions derived from the old Mach code. i provided some help
getting swap and paging working, and other bug fixes/ideas. chuck
silvers <chuq@chuq.com> also provided some other fixes.
this is the rest of the MI portion changes.
this will be KNF'd shortly. :-)
the "stream" busification functions.
In the architecture as the BeBox(CPU is big endian, have ISA bus),
These methods would be used where "raw" data needs to {read,write,set}
unchanged.
Add #ifndef __BUS_SPACE_NEED_STREAM_METHODS (define that on NetBSD/bebox),
if not define __BUS_SPACE_NEED_STREAM_METHODS,
define "stream" busification functions to normal busification functions.
This is useful in the case where an attachment's probe routine
verifies that there is indeed hardware present but something goes
"wrong" in the attach causing the device to be unusable. (Without
keeping track of this, in that case incorrect ports could be
accessed or uninitted pointers could be deferenced on open or at
other times.)
an initiator/target nexus and thus mark the correct queue (if any) a
command is on.
* If a disconnected command times out, just leave it on the nexus queue
and do nothing (for now). I need yet to decide on the strategy to
follow in this case. Note: we used to move the command to the `ready'
queue and then do nothing, which is worse.
the target still is in MSG OUT phase. We still send a message (a NO_OP)
in this case and the chip will remove ATN at the appropriate time.
Using the RSTATN command here induces a "illegal command" in some
chip revisions.
This situation only occurs if the target rejects a previous (multi-byte)
message early (by switching to MESSAGE IN and sending a MESSAGE REJECT)
before the chip has completed the entire MSG OUT transfer. ATN will
remain asserted, and the target returns to MESSAGE OUT phase.
* Account for the events above when reporting "DMA not completed"
diagnostic messages.
* Stream-line the selection code a bit, and make the DMA setup code
more like the MSG OUT & DATA XFER setup.
* Fix bug in wdc that would overflow ATAPI transfer length.
* Improve wdc probe code so that 'wdc' is probed in if present
even if there are no drives attached, and so that it works
properly even if the only device is an ATAPI slave.
* bus_space-ify.
* split the ISA attachment from the wdc driver, and remove
ISA dependencies from non-ISA files.
* claim that wd and wdc are now machine-independent (probably not
completely true, but mostly so; they at least work on arm32 and
i386).
* Various other minor fixups and cleanups, some of which were pointed
out by Kazuki Sakamoto.
- "out of resource" errors cause receive buffer chain corruption
- resets can confuse the interrupt handler
- multi-cast setup causes receive buffer chain corruption
- shared memory setup incomplete
* Enhance effiency by avoiding unnecessary shared memory access,
improved handling of receive frame & buffer descriptors, and
introducing an `asynchronous' option when issuing 82586 commands.
* Exclusively use offsets relative to the bus handle representing the shared
memory area to formulate accesses to the chip's data-structures. The
front-ends provide glue functions that cater to the chip's endian-
sensitivity, to perform the actual device access (note: single-byte
accesses are done here using `bus_space_{read,write}_1()').
This concludes the transformation into a bus-independent driver module.
* Abolish C structures to access chip data-structures; instead use macros
that take indices and offsets relative to the bus handle representing
the chip's resources.
* Include the old version of this file wholesale, until all drivers
have been updated to use the MI 82586 code.
