with large amounts of memory and not spew. This doesn't really replace
fixing this problem better later, but it works for now. Basically, if memory
is greater than 128MB, start upping the sizes of some maps.
msgbuf. Note that old 'dmesg' and 'syslogd' binaries will continue running,
though old 'dmesg' binaries will output a few bytes of junk at the start of
the buffer, and will miss a few bytes at the end of the buffer.
on EV56 and later processors that have the "amask BWX" bit clear. These
instructions will be used to implement non-swizzle bus access functions
on newer systems, such as the new AlphaStation 500s with EV56 and 21172
PCI chipsets.
See "Alpha Architecture Handbook, Version 3", DEC order number EC-QD2KB-TE.
* support chip clocks != COM_FREQ, by introducing sc_frequency (for the
mainline code) and adding a frequency parameter right after the rate
parameter to comcnattach() and com_kgdb_attach().
- Make com_isa and com_multi initialize sc_frequency to COM_FREQ.
- Make i386/machdep.c and alpha/dec_xxx.c call com*attach() with the freq.
parameter.
* supio_attach_args get two more fields: a sc_ipl and a sc_arg, both ints.
- com_supio uses the first for interupt establishment (all childs will, as
soon as they exist) and the 2nd for sc_frequency.
- drsupio passes sc_ipl alway as 5, and for the "com"s, sc_arg as 16*115200
- hyper will pass sc_ipl as 6, and sc_arg as 16 * 460800
- Fix a few bugs in the software single-stepping support code, where
VMS PALcode ops were being checked, rather than OSF/1 PALcode ops,
causing erroneous results in the "exception return" and "unconditional
branch" predicates.
- Add the BWX instructions ("ldbu", "ldwu", "stb", "stw") to the
"load" and "store" predicates.
easier to add instructions that the disassembler doesn't know about
(the opcode subfunction number is now printed).
- Add the "amask" and "implver" operate subfunctions.
- Add the "ldbu", "ldwu", "stb", and "stw" major opcodes (BWX instructions).
An IMB intruction must be executed after software or I/O devices
write into the instruction stream or modify the instruction
stream virtual address mapping, and before the new value is
fetched as an instruction.
We were missing calls to IMB after mappings were changed, which caused
systems with large I-caches (e.g. my AlphaStation 500) to fail miserably
when mapping in new pages of program text, or when context switching
(I couldn't even get the shell from init!).
reads. This is necessary because of newer AlphaStation firmware doing
the Wrong Thing with target aborts behind PCI-PCI bridges, much like they
do the Wrong Thing with master aborts. Reported by Matthias Drochner.
PCI master aborts as eb164 firmware, so use the same workaround mechanism
on all system types (clear error register's master abort bit, and check
it after accessing configuration space), not just eb164's.
This also fixes a bug on eb164's - when making the Alpha port compile
again, I made an error that caused this to not be used on eb164 systems,
either. Thanks to Matt Jacob for pointing out this goof.
