3da75bb55d
Update the list of MIPS processor revision ID. PRids of Toshiba TX3900
...
and QED R4650 comflict each other.
1998-09-26 03:29:37 +00:00
a96d8e733a
Add EESOX manufacturer ID and SCSI2 podule ID.
1998-09-26 03:29:36 +00:00
2c50ec242f
Add basic interprocessor interrupt sending and receiving code. Current
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IPI functions: HALT, IMB, TBIA, TBIAP.
XXX HALT is not yet implemented, it's just a stub.
1998-09-26 00:03:51 +00:00
78d445810b
Add an interprocessor interrupt bitmask to the cpu_softc, and publicize
...
the cpus[] array.
1998-09-26 00:01:17 +00:00
1f4921edce
- Oops, forgot to initalize the cpu_softc simplelock.
...
- Add yet another debugging printf.
1998-09-26 00:00:33 +00:00
e2aa38459c
Implement atomic quadword load-and-latch.
1998-09-25 23:59:42 +00:00
01c75223d7
Minor style tweaks.
1998-09-25 22:06:33 +00:00
eb8de83739
`eccmemctl' inadvertently got into the `mandatory' list.
1998-09-25 11:40:16 +00:00
d3ce2be01c
Don't bother printing the message from the secondary console. All it is
...
is basically the acknowledgement of the START command. Print the idle
USPACE address for now. Use the alias "apcb_backup_ksp" when setting the
backup kernel stack pointer in the secondary's boot HWPCB.
1998-09-25 03:23:50 +00:00
57e656b2ec
The processor unique value in the PCB is used as a backup kernel stack
...
pointer when booting secondary CPUs. Add an alias for it.
1998-09-25 03:21:31 +00:00
3ea9247ac8
GENERIC config file + MULTIPROCESSOR + some debugging stuff.
1998-09-25 00:46:09 +00:00
fcb0203141
First-cut at code to spin up secondary processors on a multiprocessor
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Alpha system, conditional on MULTIPROCESSOR.
NOTE: This does not yet work completely. The secondary CPU begins the
boot process, but never makes it into the cpu spinup trampoline. This
is merely a snapshot of a work-in-progress.
1998-09-24 23:28:17 +00:00
feb1d22dcc
NCPU > 1 -> MULTIPROCESSOR
1998-09-24 23:00:43 +00:00
3cde5f5817
Machine-dependent spin lock operations for Alpha, included if MULTIPROCESSOR
...
is specified.
1998-09-24 22:32:35 +00:00
91a031471d
Implement atomic test-and-set for longwords (32-bit).
1998-09-24 22:22:07 +00:00
1b04ff4897
Make prom_enter() and prom_leave() public.
1998-09-24 21:18:13 +00:00
ba6d13d876
Use the primary CPU ID on console_restart(), not hard-coded 0.
1998-09-24 21:12:43 +00:00
27569e4050
Initialize pointer to the boot CPU's interrupt register.
1998-09-24 20:38:43 +00:00
831354d6de
Add `intreg' cpuinfo offset.
1998-09-24 20:37:17 +00:00
e43333b7e7
Move if_ade* from alpha/pci/ to alpha/a12/
1998-09-24 05:36:05 +00:00
09c3723e08
Put back ahc and bha scsi HBA driver configs.
1998-09-24 05:33:41 +00:00
81ea242049
Fix include path, these days a12 header files are in alpha/a12.
1998-09-24 05:32:52 +00:00
ec4de2679b
Track tfs -> ustarfs change.
1998-09-24 05:23:58 +00:00
c69dbb3c28
Actually, yes we do know what the rpb_restart entry point is used for,
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so delete some #if 0'd code.
1998-09-24 03:39:24 +00:00
7521c309df
When setting up the hwrpb for restarts, use the primary CPU ID from the
...
hwrpb.
1998-09-24 00:30:19 +00:00
7df5ebc392
"Gee, there was already a function to do that."
1998-09-23 22:02:21 +00:00
53d42701b5
Implement a function to recompute the HWRPB checksum.
1998-09-23 21:51:04 +00:00
86f044d10e
Track changes elsewhere in the PCI interface.
1998-09-23 21:20:55 +00:00
55714d5b34
Update for vm_offset_t, vaddr_t sweep.
1998-09-23 21:17:17 +00:00
ddde99135e
A12 crossbar switch driver.
1998-09-23 21:14:58 +00:00
73fdd29a64
A12 detached console tty driver and NetBSD console interface.
1998-09-23 21:14:02 +00:00
58ab38cb69
Use per-CPU interrupt status register.
1998-09-23 11:07:28 +00:00
9eca565a37
Make cgsix_sbus & cgsix_obio dependent on their respective attribute.s
1998-09-23 08:49:46 +00:00
d6746389a4
The nmi_* routines are sun4m-only.
1998-09-23 08:44:51 +00:00
d720002637
Fix a typo in RCS keyword.
1998-09-22 16:23:20 +00:00
7c4c19c768
First pass KNF. This probably needs more work.
1998-09-22 16:01:51 +00:00
aa1cf01930
Express per-processor interrupt registers in a C structure as well.
1998-09-22 13:42:26 +00:00
bd37118769
Dup header.
1998-09-22 13:41:03 +00:00
eca50c1c33
Flush cache after diddling with trap vectors.
1998-09-22 13:40:08 +00:00
1186ba5102
Introduce a `flush entire cache' method.
1998-09-22 13:39:19 +00:00
5afb0e8bcb
Keep the per-processor interrupt status in the cpuinfo structure.
...
For now, map them to the fixed virtual addresses set up early in autoconf.c
1998-09-22 13:08:44 +00:00
5fa16c668b
Define the inter-console communication buffer portion of the per-cpu
...
info structure.
1998-09-22 08:16:51 +00:00
ec49dd71dd
Change 41 separate printf()'s into a table and 2 printf()'s.
1998-09-22 06:24:26 +00:00
6871d2529f
Add missing mb ops.
1998-09-22 06:10:53 +00:00
402a9210a2
Implement quadword atomic test-and-set.
1998-09-22 05:56:52 +00:00
c945760779
sign-extend some operand types which need it.
1998-09-22 05:40:14 +00:00
5b01d45ac4
Add a `-b #' option and logic for locating the secondary boot image via
...
an absolute block address. It's cheating, as the motivation is support for
the libsa ustar tfs `filesystem' and the solution symmetrical to ufs and
cd9660 would have been to teach installboot about tfs. However, it still
would have been different as you can't mount a tfs with the kernel, and
this option gets possibly useful support for any contiguous format, even
completely raw boot images.
1998-09-22 05:03:36 +00:00
e10cc7910d
Add some support for multiple processors to the pmap module. Still left
...
to do: TLB shootdown code, but that will be much easier to write once
the code to spin up the additional CPUs is working.
1998-09-22 03:58:10 +00:00
bc3dce964b
Declare the coda character device functions here.
1998-09-22 03:42:10 +00:00
2a4d75715c
cfs/CFS -> coda/CODA in strings.
...
Move the cdev declaration for the code filesystem to conf.h
1998-09-22 03:40:42 +00:00
nisimura