8a04118d2b
Pretty print plic attachment
2024-03-24 08:34:20 +00:00
f36002f244
Move the at-shutdown call to resettodr() from cpu_reboot() to kern_reboot().
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It's a small step, but it's a step.
2024-03-05 14:15:28 +00:00
19cd387c48
Warn about building a kernel with the wrong toolchain.
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Idea from mrg@
2024-02-25 14:27:41 +00:00
1d74d539a6
Turn off HEARTBEAT
2024-02-11 09:07:49 +00:00
100a3398b8
fix spelling mistakes, mainly in comments and log messages.
2024-02-09 22:08:30 +00:00
650a2dd4b6
s/incompatiable/incompatible/ in error messages.
2024-02-09 18:39:52 +00:00
4534f691bc
Attach ld at sdmmc
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The SD card on my Beagle-V now works. Thanks jmcneill!
2024-02-09 08:51:49 +00:00
f469c2b11c
Define _RISCV_NEED_BUS_DMA_BOUNCE.
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Pointed out as being needed by jmcneill. Thanks!
2024-02-08 18:25:58 +00:00
64a66e0276
Some fixes from Roland Illig
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- fix a locking bug
- '\n' at the end of error messages
2024-02-08 07:13:10 +00:00
e4eb1270e4
risc-v: add a driver the JH7100 pin controller
2024-02-07 17:17:59 +00:00
0dd108733b
Use <space><tab> consistently
2024-02-07 17:03:35 +00:00
90313c06e6
Remove ryo@'s mail addresses.
2024-02-07 04:20:25 +00:00
82bba4e936
fix various typos in comments.
2024-02-05 21:46:04 +00:00
f22ed7e5e6
fix various typos in comments.
2024-02-02 22:00:32 +00:00
c78676accc
PR/57889: Ricardo Branco: ext2fs does not have user immutable and append
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file flags, only system ones. Restrict those to the superuser. Before
the behavior was controlled by EXT2FS_SYSTEM_FLAGS. Make that behavior the
default.
2024-01-29 18:27:09 +00:00
a08bd3cc71
Make this compile without MULTIPROCESSOR
2024-01-21 08:48:21 +00:00
634ac1605c
Remove an empty line
2024-01-21 08:41:00 +00:00
ae8f872ccf
spaces -> tab
2024-01-21 08:39:50 +00:00
1716a55c75
Add bwfm* at sdmmc? for the Broadcom BCM43xxx WiFi Interface
2024-01-20 08:05:37 +00:00
96a48ce4bf
Add DesignWare SD/MMC attachment.
2024-01-20 08:04:35 +00:00
9679f98324
Use fdt_cpu_rootconf
2024-01-19 09:09:39 +00:00
d908d4c567
risc-v: attach the Cadence XHCI usb controller on the JH7100 SoC
2024-01-18 07:48:56 +00:00
d326e36a5f
Provide a working delay(9)
2024-01-18 07:41:50 +00:00
350efc6a70
s/FALLTHOUGH/FALLTHROUGH/ in comment.
2024-01-18 03:36:24 +00:00
f0cc90c163
Fix types of constants
2024-01-17 07:05:35 +00:00
57c36208f8
Implement jh7100_clkc_fracdiv_get_rate
2024-01-17 06:56:50 +00:00
af96d36815
risc-v: add a StarTech JH7100 SoC clock driver
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The JH7100 is seen in the Beagle-V board.
2024-01-16 09:06:46 +00:00
688f2af965
risc-v: the SiFive FU[57]40 cache controller is present in the JH71x0 SoCs.
2024-01-14 07:13:15 +00:00
73ce3dc071
risc-v: add a SiFive FU[57]40/ L2 Cache controller driver
2024-01-13 17:01:58 +00:00
d1d52dee1a
Attach generic system controllers
2024-01-13 16:43:08 +00:00
a01b373c1e
Group pass 1 attachments
2024-01-13 16:36:32 +00:00
686b1ff1b4
risc-v: probe the number of supported ASIDs
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Flush the entire TLB if no ASIDs are supported on pmap_activate.
2024-01-01 17:18:02 +00:00
f801e0a3ea
Perform more checks before establishing external interrupt handlers for
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each hart. The VisionFive2 DTS list the S7 core with status = "disabled".
2024-01-01 13:51:56 +00:00
907ef1d191
G/C ununsed and incorrect SIE_IM
2023-12-25 13:31:00 +00:00
56ebfa498e
Count interrupts across harts and their local interrupt controllers
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correctly.
2023-12-25 13:21:30 +00:00
b1f7b8d5fe
Deliver plic interrupts to the cpu^Whart establishing the interrupt
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handler. At least this is known to be a valid hart, but it might share
some interrupts around too.
2023-12-25 13:01:59 +00:00
eb6df588d1
Minor stylistic changes. NFCI.
2023-12-22 08:41:59 +00:00
c7f83ce504
Free memory on failure
2023-12-16 18:02:02 +00:00
6f5d0134ba
Not all RISC-V CPUs have ASIDs
2023-10-06 08:48:49 +00:00
68fa584377
Arrange to update cached LWP credentials in userret() rather than during
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syscall/trap entry, eliminating a test+branch on every syscall/trap.
This wasn't possible in the 3.99.x timeframe when l->l_cred came about
because there wasn't a reliable/timely way to force an ONPROC LWP running on
a remote CPU into the kernel (which is just about the only new thing in
this scheme).
2023-10-05 19:41:03 +00:00
acd53a6eea
riscv: ptrace: Add PTRACE_ILLEGAL_ASM for ATF
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All related tests successfully pass.
2023-09-14 03:25:31 +00:00
2d3abdba8d
Handle CAUSE_LOAD_PAGE_FAULT in trap_pagefault_fixup
2023-09-07 12:48:49 +00:00
6345bad4cf
Fix and enable MULTIPROCESSOR
2023-09-03 08:48:19 +00:00
71aa81fb0f
Be clear about hart vs cpu. NFCI.
2023-09-02 09:58:15 +00:00
f0efbc16f0
Simplify plic_fdt_intr_disestablish by calling plic_intr_disestablish
2023-09-02 09:29:59 +00:00
0e882f4be8
Fix a comment and enable RISC-V ddb mach commands
2023-09-02 09:27:09 +00:00
2a2623fc9c
Remove duplicate .ci_cpl initialiser.
2023-08-28 11:12:42 +00:00
ca4bf86fa8
riscv: cpu_setmcontext: Do not unconditionally update tp register
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Conserve tp register for _UC_CPU and update later if _UC_TLSBASE is
specified. This is what powerpc does, which also uses a general
purpose register for TLS pointer.
Found by tests/lib/libpthread/t_swapcontext:swapcontext1, which
successfully passes now.
2023-08-24 05:46:55 +00:00
149c01cf1c
riscv: Add PTRACE_BREAKPOINT and friends for ATF
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Since its size must be determined a priori, explicitly use
c.ebreak for sure.
Now, related tests in ATF successfully pass for riscv64,
as far as I can see.
2023-08-24 05:40:08 +00:00
ee1dd380bf
riscv/trap.c: Dump cause register for unhandled page fault
2023-08-22 07:11:15 +00:00
skrll