disable multiword DMA for these chips. multiword DMA can be forced with
options PCIIDE_AMD756_ENABLEDMA on rev D2 chips, but use at your own risk !
While I'm there remove a duplicate allocation of sc_wdcdev.nchannels in HPT
code.
- add protection mechanism against ND cache corruption due to bad NUD hints.
- more stats
- icmp6 pps limitation. TOOD: should implement ppsratecheck(9).
to machine memory size upon boot if the number has not been specified
explicitly in kernel config - at this moment, 0.5% of system
memory is used for vnodes (but minimum NVNODE vnodes)
volatile flags (isp_mboxbsy- keeps a bitmask of expected output mailbox
registers) and storage for them (isp_mboxtmp). Get rid of macroized
LUN widths. This is determined at run time.
Make lfs_uinodes a signed quantity for debugging purposes, and set it to
zero as fs mount time.
Enclose setting/clearing of the dirty flags (IN_MODIFIED, IN_ACCESSED,
IN_CLEANING) in macros, and use those macros everywhere. Make
LFS_ITIMES use these macros; updated the ITIMES macro in inode.h to know
about this. Make ufs_getattr use ITIMES instead of FFS_ITIMES.
in new MBOX_WAIT_COMPLETE/MBOX_NOTIFY_COMPLETE macros (ready for SMPizing).
Define STRNCAT inline for our usage.
Stealing a bit of the xs_status flags to maintain command state that
is pertinent for the hBA- should really reserve them for private usage
in scsipiconf.h.
Qlogic controller driven by this chipset. If they don't want the verbosity,
don't compile a DIAGNOSTIC kernel.
Major amount of mailbox command rewrites- hopefully should fix some of the
outstanding PRs.
Change header to note that this is no longer maintained at NASA/Ames.
and loaded. Remember to enable interrupts after isp_reset but before
isp_attach. Return CMD_EAGAIN on request queue overflow so we can retry
the command when there's more queue space.
in ip_mroute.c for duplicate tunnel entries, too. Well, what
really needs to happen is that the mrouting code needs to be
changed to work w/ `gif' tunnels... but...
Some AMD controllers have a bug which can look up the machine when using DMA, so
disable DMA for some revisions (info provided by AMD).
"options PCIIDE_AMD756_ENABLEDMA" can be used to force DMA on these chips.
registers. rationale:
- Netwave cards choke if we map i/o memory to >= 0x400
- even though, CIS tuple talks nothing about it
- it is not possible to specify range in pcmcia_io_map
- it would be very bad to do a try-and-error bus_space allocation for
i/o memory regions < 0x400
- we can have exactly the same functionality with memory mapped access
this should correct PR 10139.
the memory mapped access idea was from WIDE wildboar/bsdi cnw code.
hannken