counters. These counters do not exist on all CPUs, but where they
do exist, can be used for counting events such as dcache misses that
would otherwise be difficult or impossible to instrument by code
inspection or hardware simulation.
pmc(9) is meant to be a general interface. Initially, the Intel XScale
counters are the only ones supported.
- Use the CPU count register for more accurate microtime (from
sbmips) and delay (based on an evbmips delay function) functions.
- Schedule the next hardclock interrupt more accurately (from
an sgimips patch by Rafal Boni). Clock drift on one board is
now ~7ppm instead of ~330ppm.
- Purge old pmax-based mcclock code.
- Correctly round off some clock-derived variable calculations.
XXX: Some of this code should be migrated to sys/arch/mips.
MIPS32 4Kc CPU board, with support for the MIPS64 5Kc and the QED RM5261
CPU boards to follow.
The cs4281 audio hasn't been tested, there are some interrupt problems
with onboard the pciide, but all other on-board peripherals work.
The evbmips port will support more MIPS evaluation boards in the future.
