counters. These counters do not exist on all CPUs, but where they
do exist, can be used for counting events such as dcache misses that
would otherwise be difficult or impossible to instrument by code
inspection or hardware simulation.
pmc(9) is meant to be a general interface. Initially, the Intel XScale
counters are the only ones supported.
be properly used by any misc. cloning device. While here, correct
a comment to indicate that "open" is the only entry point and that
everything else is handled with fileops.
* Pull in dev/mii/files.mii from conf/files, rather than playing
the magic "files include order" dance in N machine-dependent
configuration definitions.
become ippp (ISDN ppp) and irip (ISDN raw IP). The character device now
are called: /dev/isdn (isdnd <-> kernel communication), /dev/isdnctl (dialing
and other control), /dev/isdntrc* (tracing), /dev/isdnbchan* (raw B channel
access, i.e. for user land PPP) and /dev/isdntel* (telephone devices, i.e.
for answering machines).
sequence using the reciprocal of the delay divisor to perform the
division.
Set the cp0 compare register so that it doesn't trigger interrupts and
reset the cp0 count register in the hardclock interrupt handler.
To implement a more accurate microtime using the CP0 COUNT
register we need to divide that register by the number of
cycles per MHz. But...
DIV and DIVU are expensive on MIPS (eg 75 clocks on the
R4000). MULT and MULTU are only 12 clocks on the same CPU.
On the SB1 these appear to be 40-72 clocks for DIV/DIVU and 3
clocks for MUL/MULTU.
The strategy we use to to calculate the reciprical of cycles
per MHz, scaled by 1<<32. Then we can simply issue a MULTU
and pluck of the HI register and have the results of the
division.
"swarm"). Other SB-cpu boards will be supported by this port in
the future.
Includes support for on-chip ethernet and serial. Many features
still missing - notably SMP, PCI/LDT and IDE.
This code is provided by the Broadband Processor Business Unit at
Broadcom Corp with minor updates by me.
