- Make the 32-bit SPARC profile support work with the GCC 2.95.3
SPARC ELF compiler, which uses a different name for mcount.
- Make the 64-bit SPARC profile support header look more like the 32-bit
SPARC header (no functional change -- 64-bit SPARC already used the
correct mcount name).
which have the Tekram TRM-S1040 ASIC.
This driver is written by Rui-Xiang Guo <rxg@ms25.url.com.tw>,
and a number of cosmetic changes by me.
Tested on i386 by the author, and on macppc and sparc64 by me.
XXX On arc, kernel got panic in ltsleep() called from scsipi_execute_xs(),
XXX but I'm not sure what is wrong...
file name data and the entry starts with \0\0. Apparently this happens
occasionally, don't know if it's mtools (probably), MS Windows or
NetBSD msdosfs fault. When this happens, NetBSD msdosfs was not
able to open the file, where neither mtools nor MS Windows had any
problem with it. So, it's appropriate to add this fix in any case.
we need later in the code. This fixes a fatal kernel fault in
pmap_modified_emulation if a user application tries to access a kernel
address that is section-mapped.
Add a diagnostic that detects attempts to call pmap_kenter_pa with a
va that is section-mapped.
- Set MARK_START to where we expect to be loading the kernel (0xf0100000).
- The ARM OpenFirmare bindings document describes how the client
program is loaded: OFW allocates and maps 6MB of memory at load-base
(0xf0000000), loads the client program, and then unmaps the memory from
the end of the client program to the end of the allocated region. Then
transfers control to the client program. We must emulate this behavior
to load the kernel: allocate 5MB at 0xf0100000 (where we expect to load
the kernel), load the kernel, then unmap the area after the kernel.
We can now load DHCP and load the kernel via NFS before getting the
dreaded Data Abort.
caching on for a page just because we are clearing the writable bit in
the PTE: this is incompatible with the way pmap_vac_me_harder works,
and the code in the modified emulation handler doesn't know about
recalculating the cachable attributes (nor should it, IMO).
Also, if we are invalidating a page, flush its TLB entry; for some
reason we were only doing this when clearing the Write or modified
bits.
These patches together seem to solve the random seg-faults that were
still occuring occasionally under heavy paging.
itohy