Commit Graph

127065 Commits

Author SHA1 Message Date
ozaki-r
79caf7865d Restructure rtcache_lookup2 to make it clear what it does
No functional change.
2015-04-03 05:44:13 +00:00
riastradh
e1af3960a6 Use pmap_pv(9) to remove mappings of device pages in TTM.
Adapt nouveau and radeon to do pmap_pv_track for their device pages.

Proposed on tech-kern with no objections:

https://mail-index.netbsd.org/tech-kern/2015/03/26/msg018561.html

Further background at:

https://mail-index.netbsd.org/tech-kern/2014/07/23/msg017392.html
2015-04-03 01:09:42 +00:00
riastradh
f8875b371c Use pmap_pv(9) to remove mappings of Intel graphics aperture pages.
Proposed on tech-kern with no objections:

https://mail-index.netbsd.org/tech-kern/2015/03/26/msg018561.html

Further background at:

https://mail-index.netbsd.org/tech-kern/2014/07/23/msg017392.html
2015-04-03 01:06:05 +00:00
riastradh
92df5caba4 Implement pmap_pv(9) for x86 for P->V tracking of unmanaged pages.
Proposed on tech-kern with no objections:

https://mail-index.netbsd.org/tech-kern/2015/03/26/msg018561.html
2015-04-03 01:04:23 +00:00
riastradh
369827c136 Initialize P->V tracking for unmanaged device pages in uvm_init.
Conditional on __HAVE_PMAP_PV_TRACK until we add it to all pmaps.

MI part of pmap_pv(9) change proposed on tech-kern:

https://mail-index.netbsd.org/tech-kern/2015/03/26/msg018561.html
2015-04-03 01:03:42 +00:00
jmcneill
8bead3d0f8 print chip name 2015-04-02 15:48:38 +00:00
tnn
10879eadfe attach Mobile 5th Gen. Core SMBus 2015-04-02 15:32:19 +00:00
tnn
8a13682435 regen 2015-04-02 15:10:49 +00:00
tnn
a20ad0c2fd Mobile 5th Generation Intel Core devices, from intel doc #330837-004 2015-04-02 15:08:22 +00:00
msaitoh
82761969a1 Update our ixg(4) driver up to FreeBSD r238149:
- Add TSO6 support.
- The max size in dma tag is changed from 65535 to 262140 (IXGBE_TSO_SIZE).
  The value is the same as other *BSDs. The change might cause a address
  space shortage (ixgbe_dmamap_create() might fail) on some machines.
- Fix a lot of bugs.
- Improve performance.
2015-04-02 09:26:55 +00:00
skrll
4eb8d876ba #include <sys/lwp.h> for curlwp.
The locking should really be fixed.
2015-04-02 06:23:04 +00:00
matt
4dc165175b include <sys/evcnt.h> 2015-04-02 06:17:52 +00:00
matt
e6dc2a1dc1 need to include <sys/lwp.h> 2015-04-02 06:15:40 +00:00
matt
0345ca515f Allow TPIDRPRW_IS_CURLWP to be used with MULTIPROCESSOR kernels 2015-04-02 03:22:51 +00:00
matt
6ff8df59b9 #include <sys/lwp.h> 2015-04-02 03:11:34 +00:00
matt
5a713acf44 #include <sys/percpu.h> 2015-04-02 03:11:21 +00:00
matt
b513e42af5 Don't include <machine/cpu.h> 2015-04-02 03:11:01 +00:00
khorben
1d8d50afe0 Fix for PR kern/48109 (and its duplicate kern/49807)
As provided by Takahiro HAYASHI in PR kern/48109. Additional error
registration in ipf(8) by myself. Changes tested with GENERIC and
XEN3_DOM0. Thanks!

XXX pull-up netbsd-7
2015-04-02 00:12:58 +00:00
matt
a0e8cd6797 forgot to commit this when I updated netbsd64 in gcc.
Remove LP64 specific change and use the same types
when possible for IPL32 and LP64.
2015-04-01 23:31:37 +00:00
matt
e4264474cf Add two new relocs for compressed branches. 2015-04-01 21:59:01 +00:00
matt
aa2d5871fd Add _REG_S0 2015-04-01 21:55:33 +00:00
matt
6691eaf9c2 _KMEMUSER only needs struct cpu_info 2015-04-01 21:55:03 +00:00
riastradh
7153b8dc81 Don't use dvp after vput(dvp).
Still don't understand why the fstrans_done must happen after the
vput, and that will cause trouble once we move responsibility for the
vrele and unlock outside the vop as it seems obvious we ought to do
-- it's the caller's reference, not the vop's.
2015-04-01 20:03:11 +00:00
palle
3307a96624 sun4v: Implement handling of cpu_mondo trap - from OpenBSD - tested using the Legion simulator 2015-04-01 18:38:30 +00:00
skrll
ddc1f2e3f5 Change tc_quality so that gtmr can be used for MULTIPROCESSOR now that
gtmr has been fixed.
2015-04-01 07:44:18 +00:00
matt
e259e5225a Add missing ,
constify the arrays of string pointers.
2015-04-01 06:08:39 +00:00
ozaki-r
eefc30d59b Pull out ipsec routines from ip6_input
This change reduces symbol references from netinet6 to netipsec
and improves modularity of netipsec.

No functional change is intended.
2015-04-01 02:49:44 +00:00
ozaki-r
45b7377f9c Fix wrong comments 2015-04-01 01:44:56 +00:00
christos
d926e3cf91 update with new entries from libpcap-1.7.2 2015-03-31 21:42:16 +00:00
jmcneill
3c1e6be6f8 when resetting RTL8211F, make sure to disable manual MDI mode 2015-03-31 21:01:02 +00:00
riz
afea39b2f2 Spell "Independent" correctly in cargo-culted comments. 2015-03-31 17:37:47 +00:00
skrll
ae6e5eb102 More instructions. Lots left to do. 2015-03-31 16:15:07 +00:00
matt
ea4911da8a Accept the one instruction penalty and just use PTR_LA instead of doing
the relocs ourselves.
2015-03-31 11:53:13 +00:00
matt
16946e2051 Fix botch on putting user stack pointer into trapframe. 2015-03-31 11:48:10 +00:00
riastradh
24895d95c1 Amplify that even if we fixed it now the tentacles are still stuck. 2015-03-31 11:43:05 +00:00
ozaki-r
71b1eb47ca Remove unnecessary opt_ipsec.h inclusions 2015-03-31 08:47:01 +00:00
ozaki-r
7f0bd664ae Add missing ifdef IPSEC 2015-03-31 08:44:43 +00:00
matt
1a68694ee8 Optimize the exception handle a little bit more. 2015-03-31 06:47:47 +00:00
matt
5539e041c8 Since there is only "scratch" system register for use on exception, come
up with a new scheme for its use.  Use PTR_LA, INT_S/INT_L, etc.  Disable
interrupts when returning from exceptions.  Use L_CPU(tp) to get the curcpu
pointer.

When the cpu gets an exception from kernel mode, the sscratch register will be
0 and curlwp will be in the "tp" register.  When the cpu gets an exception from
user mode, the sscratch register will be a pointer to the current lwp.

When an exception happends, the sp is atomically swapped with the sscratch
register.

	If the sp is zero, the exception was a kernel exception and the
	kernel exception path is taken: sp and sscratch are swapped again
	so sscratch is zero again and then a trapframe is allocated from
	the kernel stack.  The t1 register is saved and then the pre-trapframe
	sp is written to the trapframe.

	If sp was non-zero, the exception was from user mode.  The tp register
	is temporarily saved in L_MD_TP(sp) and sp is moved tp.  tp now
	contains a pointer to the current lwp.  A pointer to the user
	trapframe is loaded from L_MD_UTF(tp).  Then t1 is saved in the
	trapframe so it can be used.  The old sp is fetched from sscratch
	while sscratch is zeroed (indicated kernel mode).  The old sp is
	saved in the trapframe.

	Upon exiting the exception, if the exception is returning to user
	mode, the contents of tp is written to sscratch.
2015-03-31 01:30:50 +00:00
matt
234a34a18b Get curcpu() from L_CPU(tp) 2015-03-31 01:15:26 +00:00
matt
8b1d38bd25 Use sfence.vm instruction and change ptbr cse to sptbr csr 2015-03-31 01:14:57 +00:00
matt
c81fbb027b No more fatc (replaced by sfence.vm instruction). 2015-03-31 01:14:02 +00:00
matt
71a690b876 Add L_MD_TP 2015-03-31 01:12:47 +00:00
matt
9a7b236e49 Add a md_tp member to mdlwp so that the exception handler can temporarily
store the user's thread pointer before saving it in the trapframe.
2015-03-31 01:12:29 +00:00
matt
e12d196579 Define curcpu() as lwp_getcpu(curlwp) since curlwp is always in the "tp"
(thread pointer) register.
2015-03-31 01:11:41 +00:00
matt
3c142fea53 Provide struct cpu_info *lwp_getcpu(struct lwp *) inline for <machine/cpu.h>
<machine/cpu.h> is include by <sys/lwp.h> before struct lwp is defined so
it can't access members inside it.  This provides an accessor which is defined
after struct lwp is defined.
2015-03-31 01:10:02 +00:00
matt
fb7a20f006 Use -mcmodel=medany to get PICish code. 2015-03-31 01:05:52 +00:00
riastradh
e9f7453834 Write an essay explaining why ffs_write is one huge WAPBL transaction. 2015-03-31 00:22:50 +00:00
skrll
99e82b4801 Whitespace 2015-03-30 11:55:00 +00:00
skrll
94a1c6fae2 Replace an if () panic with KASSERT 2015-03-30 11:54:43 +00:00