deal with dynamic address modifier generation based on the CPU's
function code pins.
Also implement VMEbus slave mode for mvme147. (Not yet 100% working.)
in the non-MULTIPROCESSOR case (LOCKDEBUG requires it). Scheduler
lock is held upon entry to mi_switch() and cpu_switch(), and
cpu_switch() releases the lock before returning.
Largely from Bill Sommerfeld, with some minor bug fixes and
machine-dependent code hacking from me.
vme_dmamem*.
This is still a work in progress, but seems to DTRT on mvme167 so far.
TODO:
. Get VMEbus slave mode going on mvme147. This should be easy.
. Fix up the A16 slave mappings.
. Bounce buffer support. (Messy, but pretty much a `must have'.)
. Figure out how to deal with `location monitor' interrupts
within the framework. (Useful for Busnet, among other things.)
. It would be nice to make use of the VMEchip2's DMA facilities...
- Using the prom getenv function determine the correct console port
- Remove old prom function hooks
- Tidy up bootflags (remove upper case names, fixup RB_ASKNAME) as
recommended by Jaromír Doleèek
code ignore the new partition types, and look for the new "USR" partition
flag.
From SUNAGAWA Keiki <kei_sun@ba2.so-net.ne.jp> with slight changes by me.
Closes PR port-macppc/10046
as used on later arm26 system (A5000, A4, A3010, A3020, A4000).
What we have got:
...
upc0 at iobus0 base 0x010000: config state bb 87 1c 00 00
fdc at upc0 offset 0x3f4 not configured
wdc0 at upc0 offset 0x1f0
lpt0 at upc0 offset 0x278
com0 at upc0 offset 0x3f8: ns8250 or ns16450, no fifo
...
What we haven't got:
- FDC support (found, but not configured).
- Clearing lpt interrupts on arm26 systems (needs help from IOEB).
- A upc(4) manual page.
- More than minimal testing (my A3020s don't have root devices).
- A proper probe routine (arm26 can't use one anyway).
need to access this when we have the proclist locked for reading,
and thus cannot store it in the PCB (which may be swapped out).
As part of this, call pmap_activate() from cpu_switch() to switch
to the new address space, and refresh the PCB's copy of the LDT
selector from the pmap structure (see above paragraph). We need
to do this for MP support anyhow.
Fixes a "panic: spinlock_switchcheck: CPU 0 has 1 spin locks" via
gdt_compact() reported by Nathan Williams.
so that special setup functions needed for some CPUs will be run before
some things (like UVM) are inited.
Add vm_page_zero_enable = FALSE to the cyrix 6x86 case, as page zeroing
while idle causes problems.
I-sync in pmap_remove_mapping() if the old mapping had PG_EXEC, and
kick curcpu (IMB) or other CPUs (via an IPI) only if the pmap was
the kernel pmap or active on other CPUs (curcpu is handled in userret()).
- Use lazy I-sync everywhere, (hopefully) eliminating the last of the
I-sync issues for multiprocessor support.
- Eliminate some memory barriers added in a couple of previous revisions,
after some discussion on port-alpha/tech-smp.
Still some lazy I-sync optimization possibilites:
- pmap_changebit() does not need to I-sync when only write-protecting
a page.
- pmap_asn_alloc() may be able to cancel a pending lazy I-sync when a
new ASN is allocated. Need to double check against Green Book or
Brown Book.
handler to hook up device interrupts and softc callbacks.
Suggested by: Jason Thorpe and Toru Nishimura
* Fixup the indenting in a few places to conform to NetBSD style
the DMA FIFO on non block aligned writes. Not doing this causes large
writes (>4k) that are not aligned to incorrectly write 64bytes
of data every 4k interval. This only occurs on raw devices - typically
newfs fails to create a clean filesystem.
scw