Commit Graph

11 Commits

Author SHA1 Message Date
gdamore
8430838831 PCI_NETBSD_CONFIGURE should allocate (but not map) address space expansion
ROMS by default.   Full discussion at
http://mail-index.netbsd.org/tech-kern/2005/12/16/0023.html
Closes PR kern/32467
Reviewed by briggs@
2006-02-10 20:52:56 +00:00
christos
95e1ffb156 merge ktrace-lwp. 2005-12-11 12:16:03 +00:00
tsutsui
69528d1dad Allow MD PCI code to specify or disable PCI_COMMAND_PARITY_ENABLE
and PCI_CMMAND_SERR_ENABLE in MI pci_configure_bus(9).
Patch from PR kern/27423 by KIYOHARA Takashi with some changes by me,
approved by Allen Briggs.
2005-03-25 14:51:39 +00:00
perry
18db93c7f6 de-__P 2005-02-04 02:10:35 +00:00
scw
b9ca9c375c Before declaring pci_conf_interrupt(), check to see if it's
already defined as a CPP macro, which is the case for SH5 at least.
2002-09-28 10:31:02 +00:00
kleink
4691174484 Move the declaration of pci_conf_hook down to <machine/pci_machdep.h>;
a port may choose to implement it not as a function but i.e. as a
pci_chipset_tag_t function vector.
2002-02-11 17:24:00 +00:00
thorpej
636e9cd08b Add a "cacheline_size" argument to pci_configure_bus(). It is used
to set the cacheline size in the BHLC register.  This should be the
size of the largest D-cache line on a system.
2001-11-28 23:48:34 +00:00
thorpej
b1ec255377 Add a "firstbus" argument to pci_configure_bus(), indicating the
first bus number to use, rather than always assuming that we should
start at bus #0.
2001-11-09 19:29:12 +00:00
briggs
e4f8f2f2da Respect __PCI_BUS_DEVORDER.
If all devices can handle 66MHz, then use 66MHz.
Triple the number of configured I/O ranges that we can handle on a bus
  (8 was insufficient--originally didn't consider multifunction devices)
Allow one to specify which types of memory to configure, I/O, ROM, or
  MEM--for example, one could configure only ROM or only non-ROM.
Ensure that the ROM is disabled if we're not configuring it.
Only set PCI_COMMAND_IO_ENABLE/PCI_COMMAND_MEM_ENABLE if there are valid
  memory ranges configured.
2001-08-30 02:52:41 +00:00
simonb
18b2f7e6a1 Add a port to IBM's PPC405GP Reference Board (the "walnut")
by Eduardo Horvath and Simon Burge of Wasabi Systems.

IBM 4xx series CPU features:
 - New pmap and revised trap handler.
 - Support on-chip timers, PCI controller, UARTs
 - Framework for on-chip ethernet and watchdog timer.
General PowerPC features:
 - Add in-kernel PPC floating point emulation
 - New in{,4}_cksum that is between 1.5 and 5 times faster than the
   old version depending on CPU type.
General changes:
 - Kernel support for generic dbsym-style symbols.
2001-06-13 06:01:44 +00:00
briggs
c6daae9b79 Add an option (defopt) PCI_NETBSD_CONFIGURE that provides PCI bus
configuration (assignment of bus numbers, BARs, timer values,
interrupt lines, etc.).
The interface must be called from m.d. code prior to probing the bus.
It is meant to be called once for each primary (bus == 0) PCI bus in
the system.  It will configure any busses behind PCI-PCI bridges.
Section 9 man page for pci_configure_bus() will come soon.
In the meantime, sample usage is in arch/sandpoint/sandpoint/mainbus.c.
[ Reviewed by thorpej ]
2001-02-09 14:33:15 +00:00