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Author	SHA1	Message	Date
mrg	c88e94a407	remove include of <vm/vm.h>. <vm/vm.h> -> <uvm/uvm_extern.h>	2000-06-29 08:58:45 +00:00
thorpej	dc362cf369	CIA core logic with BWX enabled appears on both EV56 and PCA56. We require at least EV56 for the assembler to emit BWX opcodes, so set the arch to "ev56".	1999-12-02 19:43:25 +00:00
thorpej	d4d49905dd	Add support for using BWX for PCI config space and PCI i/o and mem space on the ALCOR2 and Pyxis. BWX is enabled iff: - It hasn't been disabled by the user (patch `cia_use_bwx' or build cia.o with the option "CIA_USE_BWX=0"), - it's enabled in CIA_CSR_CNFG, - we are running on an EV5-family processor, - BWX is in the processor's capabilities mask.	1998-06-04 21:34:45 +00:00

Author

SHA1

Message

Date

mrg

c88e94a407

remove include of <vm/vm.h>. <vm/vm.h> -> <uvm/uvm_extern.h>

2000-06-29 08:58:45 +00:00

thorpej

dc362cf369

CIA core logic with BWX enabled appears on both EV56 and PCA56. We

require at least EV56 for the assembler to emit BWX opcodes, so set
the arch to "ev56".

1999-12-02 19:43:25 +00:00

thorpej

d4d49905dd

Add support for using BWX for PCI config space and PCI i/o and mem space

on the ALCOR2 and Pyxis.  BWX is enabled iff:
- It hasn't been disabled by the user (patch `cia_use_bwx' or build cia.o
  with the option "CIA_USE_BWX=0"),
- it's enabled in CIA_CSR_CNFG,
- we are running on an EV5-family processor,
- BWX is in the processor's capabilities mask.

1998-06-04 21:34:45 +00:00

3 Commits