allows us to properly identify new Intel 45nm processors, Core i7,
Atom, and the 45nm Xeon MP.
2. Properly decode several new Intel cache descriptors, as listed in the
most recent (March 2009) edition of Intel's Application Note 485.
3. Convert decode of the various features masks to use the newly added
snprintb_m(3) routine.
Addresses my PR bin/41289
Addresses my PR bin/41290
- Add interrupt shielding (direct hardware interrupts away from the
specified CPUs). Not documented just yet but will be soon.
- Redo /dev/cpu time_t compat so no kernel changes are needed.
x86:
- Make intr_establish, intr_disestablish safe to use when !cold.
- Distribute hardware interrupts among the CPUs, instead of directing
everything to the boot CPU.
- Add MD code for interrupt sheilding. This works in most cases but there is
a bug where delivery is not accepted by an LAPIC after redistribution. It
also needs re-balancing to make things fair after interrupts are turned
back on for a CPU.
so that it can return 128KB, 256KB and 512KB properly instead of
truncated 0MB or rounded 1MB.
Problem reported by nisimura@ on port-amd64 and port-i386.
flags from CPUID 80000001_EDX. Instead, keep the extended flags
separate, in ci_feature3_flags (Intel processors already kept a
separate ci_feature3_flag value).
2. Decode/display ci_feature3_flag in a vendor-specific manner, since
the definitions are vendor-specific.
OK cegger@
Port identifycpu() to userspace. The kernel lies and reports on cpuN while
actually using the values from cpu0, but this attempts to bind itself to the
requested CPU if running as root. That doesn't work properly yet due to
kern/38588, but will do once that's fixed.
cegger