* We could overrun the eva by as much as L1SEG_SIZE-PAGE_SIZE.
* sva was advanced *twice* for each valid l3 or l2 page, causing it to get out
of sync with the PTE pointers.
"To fully support self-modifying code in any situation, it is imperative that
a CPUSHA intrcution is executed before the execution of the first self-modified
instruction. The CPUSHA instruction has the effect of ensuring that there is
no stale data iin memory, the pipeline is flushed, and instruction prefetches
are repeated and taken from external memory."
I verified that this is the only way (I can think of) to make the sigtramp
regression test work on 68040. doing cpushl dc; cinvl ic; over the affected
address range, then nop (to synchronize the pipeline) is not enough; apparently
the nop does not FLUSH the pipeline and prefetch...
Note that the 68060 UM has copied the above cited passage, but in fact this is
not true. This might be connected to the fact that the 68060 does ensure
memory access order under most conditions.
- in sbus_get_intr(), if we are not an onboard device (ie, sbus card),
encode the slot number into the sbi_pri so that we can later extract
it and use it to find the interrupt map & clear registers for this
device.
- remove "intr" support as it is really pre-sun4u only.
- don't "pause" for so long in sbus interrupt debug messages..
with the slot number being passed back from sbus_get_intr(), the FS/BE
card in an ultra2 now appears to get interrupts and gets beyond
waiting for the scsibus probe!
stub for memsize_bitmap() to use the PROM bitmap for memory information.
Add a memsize function pointer to the platform structure, and make all
existing DECstation models use memsize_scan() for now.
Interestingly, from the Ultrix cpuconf.{c,h} only the 3100 and 5400 use
a memory scan to determine available memory - all other models use the
PROM bitmap...
that should make it clear in which slot the card is expected to be in.
Isapnp is not what it seems to be on the atari (where interrupts are
hardwired to slot numbers).
